# LTC726XS8

**Linearin** · Precision OpAmps · SOIC-8L

LTC726XS8 from Linearin, in a SOIC-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output (rail-to-rail). |
| 2 | -INA | input | Inverting input of amplifier A; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 3 | +INA | input | Non-inverting input of amplifier A; same voltage range as -IN, (VS- - 0.1V) to (VS+ + 0.1V). |
| 4 | -VS | power_in | Negative power supply; total supply VS+ to VS- must not exceed 10.0 V absolute maximum. |
| 5 | +INB | input | Non-inverting input of amplifier B; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 6 | -INB | input | Inverting input of amplifier B; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 7 | OUTB | output | Amplifier B output (rail-to-rail). |
| 8 | +VS | power_in | Positive power supply; operates from 1.8 V to 5.5 V at 0 to 70 °C, 2.0 V to 5.5 V over -40 to +125 °C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Linearin |
| Package | SOIC-8L |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VOS | -0.35 | 0.1 | 0.35 | mV | LTC725, LTC726, LTC727 | 4 |
| Offset voltage drift | VOS TC |  | 1 | 2.3 | μV/℃ | TA = −40 to +125 ℃ | 4 |
| Power supply rejection ratio | PSRR | 95 | 110 |  | dB | VS = 2.0 to 5.5 V, VCM < VS+ − 2V | 4 |
| Power supply rejection ratio over temperature | PSRR | 82 |  |  | dB | TA = −40 to +125 ℃ | 4 |
| Input bias current | IB |  | 1 | 150 | pA | TA = +85 ℃ | 4 |
| Input bias current | IB |  |  | 500 | pA | TA = +125 ℃ | 4 |
| Common-mode rejection ratio | CMRR | 80 | 96 |  | dB | VS = 5.5 V, VCM = −0.1 to 5.6 V | 4 |
| Common-mode rejection ratio over temperature | CMRR | 75 |  |  | dB | VCM = 0 to 5.3 V, TA = −40 to +125 ℃ | 4 |
| Common-mode rejection ratio | CMRR | 76 | 90 |  | dB | VS = 2.0 V, VCM = −0.1 to 2.1 V | 4 |
| Common-mode rejection ratio over temperature | CMRR | 70 |  |  | dB | VCM = 0 to 1.8 V, TA = −40 to +125 ℃ | 4 |
| Open-loop voltage gain | AVOL | 97 | 105 |  | dB | RL = 10 kΩ, VO = 0.05 to 3.5 V | 4 |
| Open-loop voltage gain over temperature | AVOL | 87 |  |  | dB | RL = 10 kΩ, TA = −40 to +125 ℃ | 4 |
| Open-loop voltage gain | AVOL | 85 | 90 |  | dB | RL = 600 Ω, VO = 0.15 to 3.5 V | 4 |
| Open-loop voltage gain over temperature | AVOL | 75 |  |  | dB | RL = 600 Ω, TA = −40 to +125 ℃ | 4 |
| Operating supply voltage | VS | 1.8 |  | 5.5 | V | TA = 0 to +70 ℃ | 5 |
| Operating supply voltage | VS | 2 |  | 5.5 | V | TA = −40 to +125 ℃ | 5 |
| Quiescent current (per amplifier) | IQ |  | 625 | 760 | μA | VS = 2.0 V | 5 |
| Quiescent current (per amplifier) | IQ |  | 750 | 930 | μA | VS = 5.0 V | 5 |
| Operating temperature range | TA | -40 |  | 125 | ℃ |  | 5 |
| Supply voltage, VS+ to VS- |  |  |  | 10 | V |  | 3 |
| Signal input terminal current |  | -10 |  | 10 | mA |  | 3 |
| Storage temperature range | Tstg | -65 |  | 150 | ℃ |  | 3 |
| Junction temperature | TJ |  |  | 150 | ℃ |  | 3 |
| Lead temperature |  |  |  | 260 | ℃ | Soldering 10 sec | 3 |
| ESD human body model | HBM | -5000 |  | 5000 | V | per MIL-STD-883J / Method 3015.9 | 3 |
| ESD charged device model | CDM | -2000 |  | 2000 | V | per ESDA/JEDEC JS-002-2014 | 3 |
| ESD machine model | MM | -250 |  | 250 | V | per JESD22-A115C | 3 |
| Package thermal resistance SOIC-8L | θJA |  | 125 |  | ℃/W | SOIC-8L | 5 |
| Input offset current | IOS |  | 1 |  | pA |  | 4 |
| Input voltage noise | Vn |  | 3 |  | μVP-P | f = 0.1 to 10 Hz | 4 |
| Input voltage noise density | en |  | 19 |  | nV/√Hz | f = 100 Hz | 4 |
| Input voltage noise density | en |  | 8 |  | nV/√Hz | f = 10 kHz | 4 |
| Input current noise density | In |  | 3 |  | fA/√Hz | f = 1 kHz | 4 |
| Input capacitance, differential | CIN |  | 2 |  | pF | Differential | 4 |
| Input capacitance, common mode | CIN |  | 3.5 |  | pF | Common mode | 4 |
| Gain bandwidth product | GBW |  | 11 |  | MHz |  | 4 |
| Slew rate | SR |  | 11 |  | V/μs | G = +1, CL = 100 pF, VO = 1.5 to 3.5 V | 4 |
| Total harmonic distortion + noise | THD+N |  | 0.0005 |  | % | G = +1, f = 1 kHz, VO = 0.5 VRMS | 4 |
| Settling time | tS |  | 0.26 |  | μs | To 0.1%, G = +1, 1V step | 4 |
| Settling time | tS |  | 0.34 |  | μs | To 0.01%, G = +1, 1V step | 4 |
| Overload recovery time | tOR |  | 0.3 |  | μs | VIN * Gain > VS | 4 |
| Short-circuit current | ISC |  | 75 |  | mA |  | 5 |

## CAD (KiCad official)

- Symbol: `LTC726XS8`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8L (KiCad packages3D, STEP)
- 3D model files: `ltc726xs8-etched.step` / `ltc726xs8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc726xs8.step` / `ltc726xs8.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Linearin datasheet](docs/ltc726xs8-datasheet.pdf) (24 pp, sha256 `0ce87401a5cdef51`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ltc726xs8-datasheet.pdf)