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LTC724XT14

Public Made by Adom

by adom

Linearin Operational Amplifier, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LTC724XT14

Linearin · Operational Amplifier · TSSOP-14

LTC724XT14 from Linearin, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTA output Amplifier A output.
2 -INA input Inverting input of amplifier A, with a voltage range from (VS- - 0.1V) to (VS+ + 0.1V).
3 +INA input Non-inverting input of amplifier A, with the same voltage range as -IN.
4 +VS power_in Positive power supply, 2.0V to 5.5V between VS+ and VS- (split supplies possible).
5 +INB input Non-inverting input of amplifier B, with the same voltage range as -IN.
6 -INB input Inverting input of amplifier B, with a voltage range from (VS- - 0.1V) to (VS+ + 0.1V).
7 OUTB output Amplifier B output.
8 OUTC output Amplifier C output.
9 -INC input Inverting input of amplifier C, with a voltage range from (VS- - 0.1V) to (VS+ + 0.1V).
10 +INC input Non-inverting input of amplifier C, with the same voltage range as -IN.
11 -VS power_in Negative power supply, normally tied to ground; may be tied to another voltage as long as VS+ to VS- is 2.0V to 5.5V.
12 +IND input Non-inverting input of amplifier D, with the same voltage range as -IN.
13 -IND input Inverting input of amplifier D, with a voltage range from (VS- - 0.1V) to (VS+ + 0.1V).
14 OUTD output Amplifier D output.

Key specifications

Parameter Value
Manufacturer Linearin
Package TSSOP-14
Category Amplifiers
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS 0.5 3 mV 4
Offset voltage drift VOS TC 1 3 μV/℃ TA = −40 to +125 ℃ 4
Power supply rejection ratio PSRR 95 110 dB VS = 2.0 to 5.5 V, VCM < VS+ − 2V 4
Power supply rejection ratio (over temperature) PSRR 82 dB TA = −40 to +125 ℃ 4
Input bias current IB 150 pA TA = +85 ℃ 4
Input bias current IB 500 pA TA = +125 ℃ 4
Common-mode rejection ratio CMRR 68 84 dB VS = 5.5 V, VCM = −0.1 to 5.6 V 4
Common-mode rejection ratio (over temperature) CMRR 65 dB VCM = 0 to 5.3 V, TA = −40 to +125 ℃ 4
Common-mode rejection ratio CMRR 65 78 dB VS = 2.0 V, VCM = −0.1 to 2.1 V 4
Common-mode rejection ratio (over temperature) CMRR 62 dB VCM = 0 to 1.8 V, TA = −40 to +125 ℃ 4
Open-loop voltage gain AVOL 97 105 dB RL = 10 kΩ, VO = 0.05 to 3.5 V 4
Open-loop voltage gain (over temperature) AVOL 87 dB TA = −40 to +125 ℃ 4
Open-loop voltage gain AVOL 85 92 dB RL = 600 Ω, VO = 0.15 to 3.5 V 4
Open-loop voltage gain (over temperature) AVOL 75 dB TA = −40 to +125 ℃ 4
High output voltage swing VOH -8 -12 mV RL = 10 kΩ (printed VS+-12 / VS+-8) 5
High output voltage swing VOH -125 -180 mV RL = 600 Ω (printed VS+-180 / VS+-125) 5
Low output voltage swing VOL 5.5 8 mV RL = 10 kΩ (printed VS-+5.5 / VS-+8) 5
Low output voltage swing VOL 88 130 mV RL = 600 Ω (printed VS-+88 / VS-+130) 5
Operating supply voltage VS 1.8 5.5 V TA = 0 to +70 ℃ 5
Operating supply voltage VS 2 5.5 V TA = −40 to +125 ℃ 5
Quiescent current (per amplifier) IQ 615 740 μA VS = 2.0 V 5
Quiescent current (per amplifier) IQ 780 940 μA VS = 5.5 V 5
Operating temperature range TA -40 125 ℃ 5
Supply voltage VS+ to VS- 10 V 3
Signal input current -10 10 mA Signal input terminals 3
Storage temperature Tstg -65 150 ℃ 3
Junction temperature TJ 150 ℃ 3
Lead temperature 260 ℃ Soldering 10 sec 3
ESD HBM -5000 5000 V per MIL-STD-883J / Method 3015.9 3
ESD CDM -2000 2000 V per ESDA/JEDEC JS-002-2014 3
ESD MM -250 250 V per JESD22-A115C 3
Package thermal resistance θJA 112 ℃/W TSSOP-14L 5
Common-mode voltage range VCM -0.1 0.1 V VS--0.1 to VS++0.1 (relative to supply rails) 4
Input offset current IOS 1 pA 4
Input voltage noise Vn 3.7 μVP-P f = 0.1 to 10 Hz 4
Input voltage noise density en 8 nV/√Hz f = 1 kHz 4
Input current noise density In 5 fA/√Hz f = 1 kHz 4
Input capacitance, differential CIN 2 pF Differential 4
Input capacitance, common mode CIN 3.5 pF Common mode 4
Gain bandwidth product GBW 11 MHz 4
Slew rate SR 11.5 V/μs G = +1, CL = 100 pF, VO = 1.5 to 3.5 V 4
Total harmonic distortion + noise THD+N 0.0005 % G = +1, f = 1 kHz, VO = 0.5 VRMS 4
Settling time tS 0.26 μs To 0.1%, G = +1, 1V step 4
Settling time tS 0.34 μs To 0.01%, G = +1, 1V step 4
Overload recovery time tOR 0.3 μs VIN * Gain > VS 4
Short-circuit current ISC 70 mA +70 / -85 mA as printed 5

CAD (KiCad official)

  • Symbol: LTC724XT14
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ltc724xt14-etched.step / ltc724xt14-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc724xt14.step / ltc724xt14.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Linearin datasheet (24 pp, sha256 dc292eed19d01823, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF