component
LTC722XF8
Public Made by Adomby adom
Linearin Operational Amplifier, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
LTC722XF8
Linearin · Operational Amplifier · DFN-8-EP(2x2)
LTC722XF8 from Linearin, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output. |
| 2 | -INA | input | Inverting input of amplifier A; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 3 | +INA | input | Non-inverting input of amplifier A; same voltage range as -IN, (VS- - 0.1V) to (VS+ + 0.1V). |
| 4 | -VS | power_in | Negative power supply, normally tied to ground; may be tied to another voltage as long as VS+ to VS- is 2.0V to 5.5V. |
| 5 | +INB | input | Non-inverting input of amplifier B; same voltage range as -IN, (VS- - 0.1V) to (VS+ + 0.1V). |
| 6 | -INB | input | Inverting input of amplifier B; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 7 | OUTB | output | Amplifier B output. |
| 8 | +VS | power_in | Positive power supply, 2.0V to 5.5V; split supplies are possible as long as VS+ to VS- is 2.0V to 5.5V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin |
| Package | DFN-8-EP(2x2) |
| Category | Operational Amplifier/Comparator |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VOS | -3 | 0.5 | 3 | mV | 4 | |
| Offset voltage drift | VOS TC | -3 | 1 | 3 | μV/℃ | TA = −40 to +125 ℃ | 4 |
| Power supply rejection ratio | PSRR | 95 | 110 | dB | VS = 2.0 to 5.5 V, VCM < VS+ − 2V | 4 | |
| Power supply rejection ratio | PSRR | 82 | dB | TA = −40 to +125 ℃ | 4 | ||
| Input bias current | IB | 150 | pA | TA = +85 ℃ | 4 | ||
| Input bias current | IB | 500 | pA | TA = +125 ℃ | 4 | ||
| Common-mode voltage range | VCM | -0.1 | 0.1 | V | 4 | ||
| Common-mode rejection ratio | CMRR | 68 | 84 | dB | VS = 5.5 V, VCM = −0.1 to 5.6 V | 4 | |
| Common-mode rejection ratio | CMRR | 65 | dB | VCM = 0 to 5.3 V, TA = −40 to +125 ℃ | 4 | ||
| Common-mode rejection ratio | CMRR | 65 | 78 | dB | VS = 2.0 V, VCM = −0.1 to 2.1 V | 4 | |
| Common-mode rejection ratio | CMRR | 62 | dB | VCM = 0 to 1.8 V, TA = −40 to +125 ℃ | 4 | ||
| Open-loop voltage gain | AVOL | 97 | 105 | dB | RL = 10 kΩ, VO = 0.05 to 3.5 V | 4 | |
| Open-loop voltage gain | AVOL | 87 | dB | TA = −40 to +125 ℃ | 4 | ||
| Open-loop voltage gain | AVOL | 85 | 92 | dB | RL = 600 Ω, VO = 0.15 to 3.5 V | 4 | |
| Open-loop voltage gain | AVOL | 75 | dB | TA = −40 to +125 ℃ | 4 | ||
| Short-circuit current | ISC | -85 | 70 | mA | 5 | ||
| Operating supply voltage | VS | 1.8 | 5.5 | V | TA = 0 to +70 ℃ | 5 | |
| Operating supply voltage | VS | 2 | 5.5 | V | TA = −40 to +125 ℃ | 5 | |
| Quiescent current (per amplifier) | IQ | 615 | 740 | μA | VS = 2.0 V | 5 | |
| Quiescent current (per amplifier) | IQ | 780 | 940 | μA | VS = 5.5 V | 5 | |
| Operating temperature range | TA | -40 | 125 | ℃ | 5 | ||
| Supply voltage VS+ to VS− | 10 | V | 3 | ||||
| Signal input terminals voltage (relative to VS− / VS+) | -0.5 | 0.5 | V | 3 | |||
| Signal input terminals current | -10 | 10 | mA | 3 | |||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 3 | ||
| Junction temperature | TJ | 150 | ℃ | 3 | |||
| Lead temperature range (soldering) | 260 | ℃ | 10 sec | 3 | |||
| ESD human body model (HBM) | -5000 | 5000 | V | per MIL-STD-883J / Method 3015.9 | 3 | ||
| ESD charged device model (CDM) | -2000 | 2000 | V | per ESDA/JEDEC JS-002-2014 | 3 | ||
| ESD machine model (MM) | -250 | 250 | V | per JESD22-A115C | 3 | ||
| Package thermal resistance, DFN2x2-8L | θJA | 94 | ℃/W | 5 |
CAD (KiCad official)
- Symbol:
LTC722XF8 - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
ltc722xf8-etched.step/ltc722xf8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc722xf8.step/ltc722xf8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Linearin datasheet (24 pp, sha256
7614ef2b880e3f65, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTC722XF8
**Linearin** · Operational Amplifier · DFN-8-EP(2x2)
LTC722XF8 from Linearin, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output. |
| 2 | -INA | input | Inverting input of amplifier A; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 3 | +INA | input | Non-inverting input of amplifier A; same voltage range as -IN, (VS- - 0.1V) to (VS+ + 0.1V). |
| 4 | -VS | power_in | Negative power supply, normally tied to ground; may be tied to another voltage as long as VS+ to VS- is 2.0V to 5.5V. |
| 5 | +INB | input | Non-inverting input of amplifier B; same voltage range as -IN, (VS- - 0.1V) to (VS+ + 0.1V). |
| 6 | -INB | input | Inverting input of amplifier B; voltage range is from (VS- - 0.1V) to (VS+ + 0.1V). |
| 7 | OUTB | output | Amplifier B output. |
| 8 | +VS | power_in | Positive power supply, 2.0V to 5.5V; split supplies are possible as long as VS+ to VS- is 2.0V to 5.5V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin |
| Package | DFN-8-EP(2x2) |
| Category | Operational Amplifier/Comparator |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VOS | -3 | 0.5 | 3 | mV | | 4 |
| Offset voltage drift | VOS TC | -3 | 1 | 3 | μV/℃ | TA = −40 to +125 ℃ | 4 |
| Power supply rejection ratio | PSRR | 95 | 110 | | dB | VS = 2.0 to 5.5 V, VCM < VS+ − 2V | 4 |
| Power supply rejection ratio | PSRR | 82 | | | dB | TA = −40 to +125 ℃ | 4 |
| Input bias current | IB | | | 150 | pA | TA = +85 ℃ | 4 |
| Input bias current | IB | | | 500 | pA | TA = +125 ℃ | 4 |
| Common-mode voltage range | VCM | -0.1 | | 0.1 | V | | 4 |
| Common-mode rejection ratio | CMRR | 68 | 84 | | dB | VS = 5.5 V, VCM = −0.1 to 5.6 V | 4 |
| Common-mode rejection ratio | CMRR | 65 | | | dB | VCM = 0 to 5.3 V, TA = −40 to +125 ℃ | 4 |
| Common-mode rejection ratio | CMRR | 65 | 78 | | dB | VS = 2.0 V, VCM = −0.1 to 2.1 V | 4 |
| Common-mode rejection ratio | CMRR | 62 | | | dB | VCM = 0 to 1.8 V, TA = −40 to +125 ℃ | 4 |
| Open-loop voltage gain | AVOL | 97 | 105 | | dB | RL = 10 kΩ, VO = 0.05 to 3.5 V | 4 |
| Open-loop voltage gain | AVOL | 87 | | | dB | TA = −40 to +125 ℃ | 4 |
| Open-loop voltage gain | AVOL | 85 | 92 | | dB | RL = 600 Ω, VO = 0.15 to 3.5 V | 4 |
| Open-loop voltage gain | AVOL | 75 | | | dB | TA = −40 to +125 ℃ | 4 |
| Short-circuit current | ISC | -85 | | 70 | mA | | 5 |
| Operating supply voltage | VS | 1.8 | | 5.5 | V | TA = 0 to +70 ℃ | 5 |
| Operating supply voltage | VS | 2 | | 5.5 | V | TA = −40 to +125 ℃ | 5 |
| Quiescent current (per amplifier) | IQ | | 615 | 740 | μA | VS = 2.0 V | 5 |
| Quiescent current (per amplifier) | IQ | | 780 | 940 | μA | VS = 5.5 V | 5 |
| Operating temperature range | TA | -40 | | 125 | ℃ | | 5 |
| Supply voltage VS+ to VS− | | | | 10 | V | | 3 |
| Signal input terminals voltage (relative to VS− / VS+) | | -0.5 | | 0.5 | V | | 3 |
| Signal input terminals current | | -10 | | 10 | mA | | 3 |
| Storage temperature range | Tstg | -65 | | 150 | ℃ | | 3 |
| Junction temperature | TJ | | | 150 | ℃ | | 3 |
| Lead temperature range (soldering) | | | | 260 | ℃ | 10 sec | 3 |
| ESD human body model (HBM) | | -5000 | | 5000 | V | per MIL-STD-883J / Method 3015.9 | 3 |
| ESD charged device model (CDM) | | -2000 | | 2000 | V | per ESDA/JEDEC JS-002-2014 | 3 |
| ESD machine model (MM) | | -250 | | 250 | V | per JESD22-A115C | 3 |
| Package thermal resistance, DFN2x2-8L | θJA | | 94 | | ℃/W | | 5 |
## CAD (KiCad official)
- Symbol: `LTC722XF8`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `ltc722xf8-etched.step` / `ltc722xf8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc722xf8.step` / `ltc722xf8.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Linearin datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588945503492427776) (24 pp, sha256 `7614ef2b880e3f65`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltc722xf8-datasheet.pdf)