# LTC6820IMS#3ZZPBF

**Analog Devices** · Interface - Specialized · MSOP-16

LTC6820IMS#3ZZPBF from Analog Devices, in a MSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Device enable input: when high it forces the device to stay enabled, and when low the device enters IDLE after CS has been high for 5.7ms (MSTR high) or after no signal on IP/IM for 5.7ms (MSTR low), with logic thresholds set by VDDS. |
| 2 | MOSI | bidirectional | SPI Master Out/Slave In data, an open-drain pin that requires an external pull-up resistor to VDDS and receives master data when MSTR is high or drives the slave input when MSTR is low. |
| 3 | MISO | bidirectional | SPI Master In/Slave Out data, an open-drain pin that requires an external pull-up resistor to VDDS and drives the master input when MSTR is high or receives slave output when MSTR is low. |
| 4 | SCK | bidirectional | SPI clock that is an input which must not be pulled above VDDS when MSTR is high, or a push-pull output to the slave device when MSTR is low, requiring no external pull-up. |
| 5 | CS | bidirectional | SPI chip select that is an input which must not be pulled above VDDS when MSTR is high, or a push-pull output to the slave device when MSTR is low, requiring no external pull-up. |
| 6 | VDDS | power_in | SPI input/output supply (1.7V to 5.5V) that powers the SCK and CS output drivers and sets the input thresholds of SCK, CS, MOSI, MISO and EN; if separate from VDD, a bypass capacitor of at least 0.01µF must connect directly between VDDS and GND. |
| 7 | POL | input | SPI clock polarity configuration input that must be tied to VDD or GND. |
| 8 | PHA | input | SPI clock phase configuration input that must be tied to VDD or GND. |
| 9 | VDD | power_in | Device power supply input (2.7V to 5.5V) that requires a bypass capacitor of at least 0.01µF connected directly between VDD and GND. |
| 10 | IM | bidirectional | Isolated interface minus input/output that forms the differential pair with IP; during transmission its sink current is 20 times the current sourced from IBIAS, and the absolute maximum source/sink current for IP and IM is 30mA. |
| 11 | IP | bidirectional | Isolated interface plus input/output that forms the differential pair with IM; during transmission its sink current is 20 times the current sourced from IBIAS, and the absolute maximum source/sink current for IP and IM is 30mA. |
| 12 | MSTR | input | Master/slave selector input that must be tied to VDD for the master side of the isolated interface and to GND for the slave side. |
| 13 | SLOW | input | Slow interface selection input that must be tied to VDD for clock frequencies at or below 200kHz (or if slave devices cannot meet timing) and to GND for clock frequencies above 200kHz. |
| 14 | GND | power_in | Device ground reference for all supply and signal voltages. |
| 15 | ICMP | input | Isolated interface comparator threshold-setting input, driven from a resistor divider between IBIAS and GND, where the receiver comparator thresholds are set to 1/2 the ICMP voltage and ICMP is specified from 0.2V to 1.5V. |
| 16 | IBIAS | passive | Isolated interface current bias pin, connected to GND through a resistor divider to set output current, which sits at approximately 2V when enabled and whose capacitance must be kept below 50pF for feedback stability. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Operating Supply Voltage Range | VDD | 2.7 |  | 5.5 | V |  | 3 |
| VDDS IO Supply Voltage Range (Level Shifting) | VDDS | 1.7 |  | 5.5 | V | Affects CS, SCK, MOSI, MISO and EN pins | 3 |
| Supply Current, IDLE State (MSTR = 0V) | IDD |  | 2 | 6 | µA | MSTR = 0V | 3 |
| Supply Current, IDLE State (MSTR = VDD) | IDD |  | 1 | 3 | µA | MSTR = VDD | 3 |
| IO Supply Current | IDDS |  |  | 1 | µA | SPI Inputs and EN Pin at 0V or VDDS, SPI Outputs Unloaded | 3 |
| Voltage on IBIAS Pin, READY/ACTIVE State | VBIAS | 1.9 | 2 | 2.1 | V | READY/ACTIVE State | 3 |
| Voltage on IBIAS Pin, IDLE State | VBIAS |  | 0 |  | V | IDLE State | 3 |
| Isolated Interface Current Gain | AIB | 18 | 20 | 22 | mA/mA | VA ≤ 1.6V, IB = 1mA | 3 |
| Isolated Interface Current Gain | AIB | 18 | 20 | 24 | mA/mA | VA ≤ 1.6V, IB = 0.1mA | 3 |
| Transmitter Pulse Amplitude (VDD ≥ 3.3V) | VA | 1.6 |  |  | V | VA = /VIP, VIM/, VDD ≥ 3.3V | 3 |
| Threshold-Setting Voltage on ICMP Pin | VICMP | 0.2 |  | 1.5 | V | VTCMP = ATCMP • VICMP | 3 |
| Leakage Current on ICMP Pin | ILEAK(ICMP) | -1 |  | 1 | µA | VICMP = 0V to VDD | 3 |
| Leakage Current on IP and IM Pins | ILEAK(IP/IM) | -2 |  | 2 | µA | IDLE State, VIP = VIM = 0V to VDD | 3 |
| Receiver Comparator Threshold Voltage Gain | ATCMP | 0.4 | 0.5 | 0.6 | V/V | VCM = VDD/2 to VDD, 0.2V, VICMP = 0.2V to 1.5V | 3 |
| Receiver Input Resistance | RIN | 26 | 35 | 42 | kΩ | Single-Ended to IP or IM | 3 |
| Differential Wake-Up Voltage | VWAKE | 240 |  |  | mV | tDWELL = 240ns | 3 |
| Dwell Time at VWAKE | tDWELL | 240 |  |  | ns | VWAKE = 240mV | 3 |
| Start-Up Time After Wake Detection | tREADY |  |  | 8 | µs |  | 3 |
| Idle Time-Out Duration | tIDLE | 4 | 5.7 | 7.5 | ms |  | 3 |
| Digital Voltage Input High, EN Pin | VIH(EN) | 2 |  |  | V | VDDS = 2.7V to 5.5V | 3 |
| Digital Voltage Input Low, EN Pin | VIL(EN) |  |  | 0.8 | V | VDDS = 2.7V to 5.5V | 3 |
| Digital Voltage Output Low (MOSI, MISO, CS, SCK) | VOL |  |  | 0.2 | V | VDDS = 3.3V, sinking 3.3mA | 3 |
| Chip-Select Half-Pulse Width | t1/2PW(CS) | 120 | 150 | 180 | ns |  | 4 |
| Chip-Select Pulse Inversion Delay | tINV(CS) |  |  | 200 | ns |  | 4 |
| Chip-Select Response Delay | tDEL(CS) | 140 |  | 190 | ns |  | 4 |
| Data Half-Pulse Width | t½PW(D) | 40 | 50 | 60 | ns |  | 4 |
| Data Pulse Inversion Delay | tINV(D) |  |  | 70 | ns |  | 4 |
| Data Response Delay | tDEL(D) | 75 |  | 120 | ns |  | 4 |
| SCK Latching Edge to SCK Latching Edge (master tCLK) | tCLK | 0.5 |  |  | µs | SLOW = 0 | 4 |
| SCK Latching Edge to SCK Latching Edge (master tCLK) | tCLK | 5 |  |  | µs | SLOW = 1 | 4 |
| MOSI Setup Time Before SCK Latching Edge | t1 | 25 |  |  | ns |  | 4 |
| MOSI Hold Time After SCK Latching Edge | t2 | 25 |  |  | ns |  | 4 |
| SCK Low | t3 | 50 |  |  | ns | tCLK = t3 + t4 ≥ 0.5µs | 4 |
| SCK High | t4 | 50 |  |  | ns | tCLK = t3 + t4 ≥ 0.5µs | 4 |
| SCK Non-Latch Edge to MISO Valid | t8 |  |  | 55 | ns |  | 4 |
| isoSPI Data Recognized to SCK Latching Edge | t12 | 110 | 145 | 185 | ns | SLOW = 0 | 4 |
| isoSPI Data Recognized to SCK Latching Edge | t12 | 0.9 | 1.1 | 1.4 | µs | SLOW = 1 | 4 |
| SCK Pulse Width | t13 | 90 | 115 | 150 | ns | SLOW = 0 | 4 |
| SCK Non-Latch Edge to isoSPI Data Transmit | t14 | 115 | 145 | 190 | ns | SLOW = 0 | 4 |
| CS Falling Edge to SCK Non-Latch Edge | t15 | 90 | 120 | 160 | ns | PHA = 1, SLOW = 0 | 4 |
| CS Falling Edge to isoSPI Data Transmit | t16 | 200 | 265 | 345 | ns | SLOW = 0 | 4 |
| CS Falling Edge to isoSPI Data Transmit | t16 | 1.8 | 2.2 | 2.8 | µs | SLOW = 1 | 4 |
| CS Rising Edge to SCK Latching Edge | t17 | 90 | 120 | 160 | ns | PHA = 1, SLOW = 0 | 4 |
| CS Rising Edge to MOSI Rising Edge | t18 |  |  | 35 | ns |  | 4 |
| Data Return Delay | tRTN | 485 |  | 625 | ns | SLOW = 0 | 4 |
| Data Return Delay | tRTN | 3.3 |  | 4 | µs | SLOW = 1 | 4 |
| Input Supply Voltages (VDD and VDDS) to GND | VDD, VDDS |  |  | 6 | V |  | 2 |
| Pin Voltage, SCK, CS, EN |  | -0.3 |  | 6 | V | Upper limit VDDS + 0.3V (6V max) | 2 |
| Pin Voltage, IBIAS, SLOW, IP, IM |  | -0.3 |  | 6 | V | Upper limit VDD + 0.3V (6V max) | 2 |
| Pin Voltage, All Other Pins |  | -0.3 |  | 6 | V |  | 2 |
| Maximum Source/Sink Current, MOSI, MISO, SCK, CS |  |  |  | 20 | mA |  | 2 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 2 |
| Operating Temperature Range (LTC6820I) |  | -40 |  | 85 | °C | LTC6820I, the grade of LTC6820IMS#3ZZPBF | 2 |
| Maximum Junction Temperature (TJMAX) | TJMAX |  |  | 150 | °C | MS16 (MSOP) package | 2 |
| Isolated Interface Bias Resistor RBIAS | RBIAS | 2 |  | 20 | kΩ | 1% or better tolerance (Note 6) | 3 |
| Thermal Resistance, Junction to Ambient | θJA |  | 120 |  | °C/W | MS16 (16-lead plastic MSOP) package | 2 |

## CAD (KiCad official)

- Symbol: `LTC6820IMS#3ZZPBF`
- Footprint: `Package_SO:MSOP-16_3x4.039mm_P0.5mm`
- 3D model: MSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ltc6820ims-3zzpbf-etched.step` / `ltc6820ims-3zzpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc6820ims-3zzpbf.step` / `ltc6820ims-3zzpbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908170496651265) (30 pp, sha256 `81e209e79f6c137d`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ltc6820ims-3zzpbf-datasheet.pdf)