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LTC6820HMS#3ZZPBF
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Analog Devices Interface - Specialized, MSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTC6820HMS#3ZZPBF
Analog Devices · Interface - Specialized · MSOP-16
LTC6820HMS#3ZZPBF from Analog Devices, in a MSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Device enable input: high forces the device to stay enabled, low lets it enter IDLE mode after CS has been high for 5.7ms (MSTR high) or after no signal on IP/IM for 5.7ms (MSTR low), and it wakes less than 8µs after CS falls or a signal is detected on IP/IM. |
| 2 | MOSI | bidirectional | SPI Master Out/Slave In data; the output is open drain, so an external pull-up resistor to VDDS is required. |
| 3 | MISO | bidirectional | SPI Master In/Slave Out data; the output is open drain, so an external pull-up resistor to VDDS is required. |
| 4 | SCK | bidirectional | SPI clock input when MSTR is high (must not be pulled above VDDS) or push-pull clock output when MSTR is low, requiring no external pull-up. |
| 5 | CS | bidirectional | SPI chip select input when MSTR is high (must not be pulled above VDDS) or push-pull output when MSTR is low, requiring no external pull-up. |
| 6 | VDDS | power_in | SPI input/output supply (1.7V to 5.5V) that powers the SCK and CS output drivers and sets the input thresholds of SCK, CS, MOSI, MISO and EN; if separate from VDD, connect a bypass capacitor of at least 0.01µF directly between VDDS and GND. |
| 7 | POL | input | SPI clock polarity input that must be tied to VDD or GND. |
| 8 | PHA | input | SPI clock phase input that must be tied to VDD or GND. |
| 9 | VDD | power_in | Device power supply input (2.7V to 5.5V); connect a bypass capacitor of at least 0.01µF directly between VDD and GND. |
| 10 | IM | bidirectional | Isolated interface minus input/output; IP and IM maximum source/sink current is 30mA. |
| 11 | IP | bidirectional | Isolated interface plus input/output; IP and IM maximum source/sink current is 30mA. |
| 12 | MSTR | input | Master/slave selector: tie to VDD if the device is on the master side of the isolated interface and to GND if on the slave side. |
| 13 | SLOW | input | Slow interface selection: tie to VDD for clock frequencies at or below 200kHz (or if slave devices cannot meet timing), and to GND for clock frequencies above 200kHz. |
| 14 | GND | power_in | Device ground. |
| 15 | ICMP | input | Isolated interface comparator voltage threshold set: tie to the resistor divider between IBIAS and GND; the comparator thresholds are set to 1/2 the voltage on this pin. |
| 16 | IBIAS | passive | Isolated interface current bias: tie to GND through a resistor divider to set output current (about 2V when enabled, sink current on IP/IM is 20 times the IBIAS current), and limit capacitance to less than 50pF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Operating Supply Voltage Range | VDD | 2.7 | 5.5 | V | 3 | ||
| VDDS IO Supply Voltage Range (Level Shifting) | VDDS | 1.7 | 5.5 | V | Affects CS, SCK, MOSI, MISO and EN Pins | 3 | |
| Supply Current, READY/ACTIVE States | IDD | 4 | 4.8 | mA | RBIAS = 2kΩ (IB = 1mA), 1/tCLK = 0MHz | 3 | |
| Supply Current, READY/ACTIVE States | IDD | 5.8 | 7 | mA | RBIAS = 2kΩ (IB = 1mA), 1/tCLK = 1MHz | 3 | |
| Supply Current, READY/ACTIVE States | IDD | 1.3 | 2 | mA | RBIAS = 20kΩ (IB = 0.1mA), 1/tCLK = 0MHz | 3 | |
| Supply Current, READY/ACTIVE States | IDD | 2.4 | 2.9 | mA | RBIAS = 20kΩ (IB = 0.1mA), 1/tCLK = 1MHz | 3 | |
| Supply Current, IDLE State | IDD | 2 | 6 | µA | MSTR = 0V | 3 | |
| Supply Current, IDLE State | IDD | 1 | 3 | µA | MSTR = VDD | 3 | |
| IO Supply Current | IDDS | 1 | µA | SPI Inputs and EN Pin at 0V or VDDS, SPI Outputs Unloaded | 3 | ||
| Voltage on IBIAS Pin, READY/ACTIVE State | VBIAS | 1.9 | 2 | 2.1 | V | READY/ACTIVE State | 3 |
| Isolated Interface Current Gain | AIB | 18 | 20 | 22 | mA/mA | VA ≤ 1.6V, IB = 1mA | 3 |
| Isolated Interface Current Gain | AIB | 18 | 20 | 24 | mA/mA | VA ≤ 1.6V, IB = 0.1mA | 3 |
| Transmitter Pulse Amplitude | VA | 1.6 | V | VA = /VIP, VIM/, VDD ≥ 3.3V | 3 | ||
| Threshold-Setting Voltage on ICMP Pin | VICMP | 0.2 | 1.5 | V | 3 | ||
| Leakage Current on ICMP Pin | ILEAK(ICMP) | -1 | 1 | µA | VICMP = 0V to VDD | 3 | |
| Leakage Current on IP and IM Pins | ILEAK(IP/IM) | -2 | 2 | µA | IDLE State, VIP = VIM = 0V to VDD | 3 | |
| Receiver Comparator Threshold Voltage Gain | ATCMP | 0.4 | 0.5 | 0.6 | V/V | VCM = VDD/2 to VDD, 0.2V, VICMP = 0.2V to 1.5V | 3 |
| Receiver Input Resistance | RIN | 26 | 35 | 42 | kΩ | Single-Ended to IP or IM | 3 |
| Differential Wake-Up Voltage | VWAKE | 240 | mV | tDWELL = 240ns | 3 | ||
| Dwell Time at VWAKE | tDWELL | 240 | ns | VWAKE = 240mV | 3 | ||
| Start-Up Time After Wake Detection | tREADY | 8 | µs | 3 | |||
| Idle Time-Out Duration | tIDLE | 4 | 5.7 | 7.5 | ms | 3 | |
| Digital Voltage Input High, EN Pin | VIH(EN) | 2 | V | VDDS = 2.7V to 5.5V | 3 | ||
| Digital Voltage Input Low, EN Pin | VIL(EN) | 0.8 | V | VDDS = 2.7V to 5.5V | 3 | ||
| Digital Voltage Output Low (MOSI, MISO, CS, SCK) | VOL | 0.2 | V | VDDS = 3.3V, Sinking 3.3mA | 3 | ||
| Digital Pin Input Leakage Current | ILEAK(DIG) | -1 | 1 | µA | PHA, POL, MSTR, SLOW = 0V to VDD; CS, SCK, MOSI, MISO, EN = 0V to VDDS | 4 | |
| Chip-Select Half-Pulse Width | t1/2PW(CS) | 120 | 150 | 180 | ns | 4 | |
| Chip-Select Pulse Inversion Delay | tINV(CS) | 200 | ns | 4 | |||
| Chip-Select Response Delay | tDEL(CS) | 140 | 190 | ns | 4 | ||
| Data Half-Pulse Width | t½PW(D) | 40 | 50 | 60 | ns | 4 | |
| Data Pulse Inversion Delay | tINV(D) | 70 | ns | 4 | |||
| Data Response Delay | tDEL(D) | 75 | 120 | ns | 4 | ||
| SCK Latching Edge to SCK Latching Edge (tCLK) | tCLK | 0.5 | µs | SLOW = 0 | 4 | ||
| SCK Latching Edge to SCK Latching Edge (tCLK) | tCLK | 5 | µs | SLOW = 1 | 4 | ||
| MOSI Setup Time Before SCK Latching Edge | t1 | 25 | ns | 4 | |||
| MOSI Hold Time After SCK Latching Edge | t2 | 25 | ns | 4 | |||
| SCK Low | t3 | 50 | ns | tCLK = t3 + t4 ≥ 0.5µs | 4 | ||
| SCK High | t4 | 50 | ns | tCLK = t3 + t4 ≥ 0.5µs | 4 | ||
| SCK Non-Latch Edge to MISO Valid | t8 | 55 | ns | 4 | |||
| SCK Latching Edge to Short ±1 Transmit | t9 | 50 | ns | 4 | |||
| CS Rising Edge to MISO Rising | t11 | 55 | ns | 4 | |||
| isoSPI Data Recognized to SCK Latching Edge | t12 | 110 | 145 | 185 | ns | SLOW = 0 | 4 |
| isoSPI Data Recognized to SCK Latching Edge | t12 | 0.9 | 1.1 | 1.4 | µs | SLOW = 1 | 4 |
| CS Falling Edge to isoSPI Data Transmit | t16 | 200 | 265 | 345 | ns | SLOW = 0 | 4 |
| CS Falling Edge to isoSPI Data Transmit | t16 | 1.8 | 2.2 | 2.8 | µs | SLOW = 1 | 4 |
| CS Rising Edge to MOSI Rising Edge | t18 | 35 | ns | 4 | |||
| Data Return Delay | tRTN | 485 | 625 | ns | SLOW = 0 | 4 | |
| Data Return Delay | tRTN | 3.3 | 4 | µs | SLOW = 1 | 4 | |
| Input Supply Voltages (VDD and VDDS) to GND | VDD, VDDS | 6 | V | to GND | 2 | ||
| Pin Voltages, SCK, CS, EN | VSCK, VCS, VEN | -0.3 | 6 | V | Max VDDS + 0.3V, 6V max | 2 | |
| Pin Voltages, IBIAS, SLOW, IP, IM | VIBIAS, VSLOW, VIP, VIM | -0.3 | 6 | V | Max VDD + 0.3V, 6V max | 2 | |
| All Other Pin Voltages | -0.3 | 6 | V | 2 | |||
| Maximum Source/Sink Current, MOSI, MISO, SCK, CS | 20 | mA | 2 | ||||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Operating Temperature Range, LTC6820H | -40 | 125 | °C | 2 | |||
| Maximum Junction Temperature (TJMAX) | TJMAX | 150 | °C | MS package | 2 | ||
| Thermal Resistance, Junction to Ambient (θJA) | θJA | 120 | °C/W | MS package | 2 |
CAD (KiCad official)
- Symbol:
LTC6820HMS#3ZZPBF - Footprint:
Package_SO:MSOP-16_3x4.039mm_P0.5mm - 3D model: MSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ltc6820hms-3zzpbf-etched.step/ltc6820hms-3zzpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc6820hms-3zzpbf.step/ltc6820hms-3zzpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (30 pp, sha256
81e209e79f6c137d, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).