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LTC6813HLWE-1#3ZZPBF

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Analog Devices Battery Management, LQFP-64-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LTC6813HLWE-1#3ZZPBF

Analog Devices · Battery Management · LQFP-64-EP(10x10)

LTC6813HLWE-1#3ZZPBF from Analog Devices, in a LQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive supply pin; absolute maximum V+ to V- is 112.5V and V+ to C12 is 50V.
2 C18 input Cell input for the top cell of the stack; C18 to V- is limited to -0.3V to MIN(V+ + 5.5V, 112.5V) and C18 to C15 to 21V.
3 S18 bidirectional Balance input/output for cell 18; an internal N-MOSFET between S18 and C17 discharges the cell, with S(n) limited to -0.3V to MIN(8·n, 112.5V) relative to V-.
4 C17 input Cell input C17, with C(n) to C(n-1) limited to 8V and C(n) to V- limited to MIN(8·n, 112.5V).
5 S17 bidirectional Balance input/output for cell 17, connected through an internal N-MOSFET between S17 and C16 for cell discharge.
6 C16 input Cell input C16, with C(n) to C(n-1) limited to 8V.
7 S16 bidirectional Balance input/output for cell 16, connected through an internal N-MOSFET between S16 and C15 for cell discharge.
8 C15 input Cell input C15, with C(n) to C(n-1) limited to 8V.
9 S15 bidirectional Balance input/output for cell 15, connected through an internal N-MOSFET between S15 and C14 for cell discharge.
10 C14 input Cell input C14, with C(n) to C(n-1) limited to 8V.
11 S14 bidirectional Balance input/output for cell 14, connected through an internal N-MOSFET between S14 and C13 for cell discharge.
12 C13 input Cell input C13, with C(n) to C(n-1) limited to 8V.
13 S13 bidirectional Balance input/output for cell 13, connected through an internal N-MOSFET between S13 and C12 for cell discharge.
14 C12 input Cell input C12, with C(n) to C(n-1) limited to 8V; V+ to C12 is limited to 50V.
15 S12 bidirectional Balance input/output for cell 12, connected through an internal N-MOSFET between S12 and C11 for cell discharge.
16 C11 input Cell input C11, with C(n) to C(n-1) limited to 8V.
17 S11 bidirectional Balance input/output for cell 11, connected through an internal N-MOSFET between S11 and C10 for cell discharge.
18 C10 input Cell input C10, with C(n) to C(n-1) limited to 8V.
19 S10 bidirectional Balance input/output for cell 10, connected through an internal N-MOSFET between S10 and C9 for cell discharge.
20 C9 input Cell input C9, with C(n) to C(n-1) limited to 8V.
21 S9 bidirectional Balance input/output for cell 9, connected through an internal N-MOSFET between S9 and C8 for cell discharge.
22 C8 input Cell input C8, with C(n) to C(n-1) limited to 8V.
23 S8 bidirectional Balance input/output for cell 8, connected through an internal N-MOSFET between S8 and C7 for cell discharge.
24 C7 input Cell input C7, with C(n) to C(n-1) limited to 8V.
25 S7 bidirectional Balance input/output for cell 7, connected through an internal N-MOSFET between S7 and C6 for cell discharge.
26 C6 input Cell input C6, with C(n) to C(n-1) limited to 8V.
27 S6 bidirectional Balance input/output for cell 6, connected through an internal N-MOSFET between S6 and C5 for cell discharge.
28 C5 input Cell input C5, with C(n) to C(n-1) limited to 8V.
29 S5 bidirectional Balance input/output for cell 5, connected through an internal N-MOSFET between S5 and C4 for cell discharge.
30 C4 input Cell input C4, with C(n) to C(n-1) limited to 8V.
31 S4 bidirectional Balance input/output for cell 4, connected through an internal N-MOSFET between S4 and C3 for cell discharge.
32 C3 input Cell input C3, with C(n) to C(n-1) limited to 8V.
33 S3 bidirectional Balance input/output for cell 3, connected through an internal N-MOSFET between S3 and C2 for cell discharge.
34 C2 input Cell input C2, with C(n) to C(n-1) limited to 8V.
35 S2 bidirectional Balance input/output for cell 2, connected through an internal N-MOSFET between S2 and C1 for cell discharge.
36 C1 input Cell input C1, with C(n) to C(n-1) limited to 8V.
37 S1 bidirectional Balance input/output for cell 1, connected through an internal N-MOSFET between S1 and C0 for cell discharge.
38 C0 input Cell input C0 (bottom of stack reference); absolute input voltage relative to V- is -0.3V to 6V.
39 GPIO1 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
40 GPIO2 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
41 GPIO3 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V; can serve as part of an I2C or SPI port.
42 GPIO4 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V; can serve as part of an I2C or SPI port.
43 GPIO5 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V; can serve as part of an I2C or SPI port.
44 GPIO6 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
45 GPIO7 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
46 GPIO8 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
47 GPIO9 bidirectional General purpose I/O usable as digital input or output, or as an analog input with measurement range V- to 5V.
48 VREG power_out 5V regulator pin; bypass with an external 1μF capacitor.
49 DRIVE output Base drive for an external NPN whose collector connects to V+ and emitter to VREG; absolute maximum voltage is -0.3V to 7V.
50 VREF2 power_out Buffered second reference voltage for driving multiple 10k thermistors; bypass with an external 1μF capacitor.
51 VREF1 passive ADC reference voltage; bypass with an external 1μF capacitor and allow no DC loads.
52 DTEN input Discharge timer enable; connect to VREG to enable the discharge timer.
53 SDI (NC) input Serial data in for 4-wire SPI when ISOMD is tied to V-; when ISOMD is tied to VREG this pin is not connected.
54 SDO (NC) output Serial data out, an open-drain NMOS output requiring a 5k pull-up resistor when ISOMD is tied to V-; not connected when ISOMD is tied to VREG.
55 ISOMD input Serial interface mode select: connect to VREG for 2-wire isoSPI mode or to V- for 4-wire SPI mode.
56 WDT output Watchdog timer output, an open-drain NMOS that can be left unconnected or pulled to VREG through 1M; goes high impedance if no valid command is received within 2 seconds.
57 IBIAS passive isoSPI current bias; tie to V- through a resistor divider so that IBIAS is 2V when isoSPI is enabled and the driver output current is 20 times the IBIAS current.
58 ICMP passive isoSPI comparator threshold set; tie to a resistor divider between IBIAS and V- so receiver comparator thresholds are half the ICMP voltage.
59 V- power_in Negative supply pin; V- pins must be shorted together externally to the IC.
60 V- power_in Negative supply pin; V- pins must be shorted together externally to the IC, and this pin is marked as one that must be connected to V-.
61 CSB (IMA) bidirectional Active-low chip select (CSB) input when ISOMD is tied to V-; isoSPI Port A minus (IMA) differential pin when ISOMD is tied to VREG.
62 SCK (IPA) bidirectional Serial clock (SCK) input when ISOMD is tied to V-; isoSPI Port A plus (IPA) differential pin when ISOMD is tied to VREG.
63 IMB bidirectional isoSPI Port B minus (IMB) differential input/output pin.
64 IPB bidirectional isoSPI Port B plus (IPB) differential input/output pin.
65 V- power_in Exposed pad, which is V- and must be soldered to the PCB.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64-EP(10x10)
Category Power Management (PMIC)
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Total Supply Voltage V+ to V- 112.5 V 3
Supply Voltage (Relative to C12) V+ to C12 50 V 3
Input Voltage C0 (relative to V-) -0.3 6 V 3
Input Voltage C18 (relative to V-) -0.3 V Max printed as MIN (V+ + 5.5V, 112.5V) 3
Input Voltage C(n), S(n) (relative to V-) -0.3 V Max printed as MIN (8 • n, 112.5V) 3
Input Voltage IPA, IMA, IPB, IMB (relative to V-) -0.3 V Max printed as VREG + 0.3V, ≤ 6V 3
Input Voltage DRIVE -0.3 7 V 3
Input Voltage All Other Pins -0.3 6 V 3
Voltage Between Inputs C(n) to C(n-1), S(n) to C(n-1) -0.3 8 V 3
Voltage Between Inputs C18 to C15, C15 to C12, C12 to C9, C9 to C6, C6 to C3, C3 to C0 -0.3 21 V 3
Current In/Out of Pins (all except VREG, IPA, IMA, IPB, IMB, C(n), S(n)) 10 mA 3
Current In/Out of IPA, IMA, IPB, IMB 30 mA 3
Storage Temperature Range -65 150 °C 3
Junction Temperature 150 °C 3
Specified Junction Temperature Range (LTC6813H-1) -40 125 °C 3
Thermal Resistance Junction-to-Ambient θJA 17 °C/W LWE package, TJMAX = 150°C 3
Thermal Resistance Junction-to-Case θJC 2.5 °C/W LWE package 3
V+ Supply Voltage 16 60 90 V TME specifications met, over temperature range 6
VREG Supply Voltage VREG 4.5 5 5.5 V TME supply rejection < 1mV/V, over temperature range 6
VREGD Digital Supply Voltage VREGD 2.7 3 3.6 V Over temperature range 6
DRIVE Output Voltage 5.1 5.7 6.1 V Sourcing 500µA, over temperature range 6
DRIVE Output Voltage 5.4 5.7 5.9 V Sourcing 1µA, over temperature range 6
VREF1 1st Reference Voltage VREF1 3 3.15 3.3 V VREF1 pin, no load, over temperature range 5
VREF2 2nd Reference Voltage VREF2 2.993 3 3.007 V VREF2 pin, no load, over temperature range 5
VREF2 2nd Reference Voltage VREF2 2.992 3 3.008 V VREF2 pin, 5k load to V-, over temperature range 5
V+ Supply Current, Sleep (VREG = 0V) IVP 6.1 11 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 0V 4
V+ Supply Current, Sleep (VREG = 0V) IVP 6.1 18 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 0V, over temperature range 4
V+ Supply Current, Sleep (VREG = 5V) IVP 3 5 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 5V 4
V+ Supply Current, Sleep (VREG = 5V) IVP 3 9 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 5V, over temperature range 4
VREG Supply Current, Sleep (VREG = 5V) IREG(CORE) 3.1 6 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 5V 6
VREG Supply Current, Sleep (VREG = 5V) IREG(CORE) 3.1 9 µA State: Core = SLEEP, isoSPI = IDLE, VREG = 5V, over temperature range 6
VREG Supply Current, Measure IREG(CORE) 14 15 16 mA State: Core = MEASURE, over temperature range 6
Watch Dog Timer Pin Low VOL(WDT) 0.4 V WDT pin sinking 4mA, over temperature range 6
General Purpose I/O Pin Low VOL(GPIO) 0.4 V GPIO pin sinking 4mA (used as digital output), over temperature range 6
Digital Output Low SDO VOL(SDO) 0.3 V SDO sinking 1mA, over temperature range 7
SPI Pin Digital Input Voltage High VIH(SPI) 2.3 V Pins CSB, SCK, SDI, over temperature range 7
SPI Pin Digital Input Voltage Low VIL(SPI) 0.8 V Pins CSB, SCK, SDI, over temperature range 7
Configuration Pin Digital Input Voltage High VIH(CFG) 2.7 V Pins ISOMD, DTEN, GPIO1 to GPIO9, over temperature range 7
Configuration Pin Digital Input Voltage Low VIL(CFG) 1.2 V Pins ISOMD, DTEN, GPIO1 to GPIO9, over temperature range 7
Digital Input Current ILEAK(DIG) -1 1 µA Pins CSB, SCK, SDI, ISOMD, DTEN, over temperature range 7
Discharge Switch ON Resistance 4 10 Ω VCELL = 3.6V, over temperature range 6
Input Current During Open Wire Detection 70 100 130 µA Over temperature range 5
Input Current When Inputs Are Being Measured -1 1 µA State: Core = MEASURE, C(n) n = 0 to 18 5
Input Leakage Current When Inputs Are Not Being Measured IL -250 250 nA C(n) n = 0 to 18, over temperature range 5
Input Range C0 0 1 V C0, over temperature range 5
Input Range GPIO(n) 0 5 V GPIO(n) n = 1 to 9, over temperature range 5
Total Measurement Error (TME) in Normal Mode -0.2 0.2 mV C(n) to C(n-1), GPIO(n) to V- = 0 4
Total Measurement Error (TME) in Normal Mode -1.6 1.6 mV C(n) to C(n-1) = 2.0 4
Total Measurement Error (TME) in Normal Mode -2 2 mV C(n) to C(n-1), GPIO(n) to V- = 2.0, LTC6813H 4
Total Measurement Error (TME) in Normal Mode -2.2 2.2 mV C(n) to C(n-1) = 3.3 4
Total Measurement Error (TME) in Normal Mode -3.3 3.3 mV C(n) to C(n-1), GPIO(n) to V- = 3.3, LTC6813H 4
Total Measurement Error (TME) in Normal Mode -2.8 2.8 mV C(n) to C(n-1) = 4.2 4
Total Measurement Error (TME) in Normal Mode -4.2 4.2 mV C(n) to C(n-1), GPIO(n) to V- = 4.2, LTC6813H 4
Total Measurement Error (TME) in Normal Mode -1 1 mV C(n) to C(n-1), GPIO(n) to V- = 5.0 4
Sum of All Cells (Normal Mode) -0.35 0.35 % Over temperature range 4
Measurement + Calibration Cycle Time, Normal Mode tCYCLE 1743 2343 2488 µs Measure 18 Cells, starting from REFUP state, over temperature range 6
Measurement + Calibration Cycle Time, Filtered Mode tCYCLE 150 201.3 213.8 ms Measure 18 Cells, starting from REFUP state, over temperature range 6
Measurement + Calibration Cycle Time, Fast Mode tCYCLE 834 1121 1191 µs Measure 18 Cells, starting from REFUP state, over temperature range 6
Isolated Interface Bias Current IB 0.1 1 mA RBIAS = 2k to 20k, over temperature range 7

CAD (KiCad official)

  • Symbol: LTC6813HLWE-1#3ZZPBF
  • Footprint: Package_QFP:LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm
  • 3D model: LQFP-64-EP(10x10) (KiCad packages3D, STEP)
  • 3D model files: ltc6813hlwe-1-3zzpbf-etched.step / ltc6813hlwe-1-3zzpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc6813hlwe-1-3zzpbf.step / ltc6813hlwe-1-3zzpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (90 pp, sha256 8750492fd8f364bf, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF