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LTC4366CTS8-2#TRMPBF

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Analog Devices Surge Suppressors, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttvs-fuse-board level protectionltc4366cts8-2#trmpbffactory-2.0.0extractor-text

Verified LTC4366CTS8-2#TRMPBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LTC4366CTS8-2#TRMPBF · TSOT-23-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C580885, digikey 505-LTC4366CTS8-2#TRMPBFTR-ND, mouser 584-C4366CTS8-2TMPF
  • ✓family: TSOT-23-8
  • ✓files: 6 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lutoukab/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 1 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 1 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ltc4366cts8-2-trmpbf.kicad_sym✓ ltc4366cts8-2-trmpbf.kicad_mod✓ ltc4366cts8-2-trmpbf.step
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Ray Publish 0.1.0 0f71fb2 10d ago

LTC4366CTS8-2#TRMPBF

Analog Devices · Surge Suppressors · TSOT-23-8

LTC4366CTS8-2#TRMPBF from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Start-up supply input for the 7.5µA start-up current source that charges the external MOSFET gate, clamped at 12V above VSS, and must not be bypassed with a capacitor.
2 SD input Shutdown comparator input that trips 1.5V below VDD with 280mV hysteresis and must stay below the threshold for 700µs to enter shutdown; tie to VDD if unused.
3 TIMER input Timer input where a capacitor to VSS sets an overvoltage regulation period of 311ms/µF, and leaving it open gives a 1µs period before fault-off.
4 VSS power_in Device return and substrate, to which the TIMER and OUT capacitors must be returned.
5 BASE output Base driver output for an external PNP shunt regulator, connected to the anode of an internal 6.2V Zener with cathode tied to OUT, and tied to VSS if unused.
6 FB input Overvoltage regulation amplifier feedback input, driven from an external resistive divider from OUT to ground to regulate FB at 1.23V below OUT.
7 OUT power_in Charge pump and overvoltage amplifier supply input, clamped at 5.7V and requiring a 0.22µF or greater bypass to VSS.
8 GATE output Gate drive for the external N-channel MOSFET, charged by a 7.5µA start-up source and driven to 12V above OUT by the charge pump, with a 200mA pull-down during fast overvoltage events.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSOT-23-8
Category TVS/Fuse/Board Level Protection
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Shunt Regulator Voltage VZ(VDD) 11 11.7 12.5 V I = 1mA 4
VDD Shunt Regulator Load Regulation ∆VZ(VDD) 60 130 mV I = 1mA to 5mA 4
VDD Supply Voltage VDD 4.5 V Note 3 4
OUT Supply Voltage OUT 3 V Note 3 4
OUT Shunt Regulator Voltage VZ(OUT) 5 5.5 6 V I = 1mA, BASE = 0V 4
OUT Shunt Regulator Load Regulation ∆VZ(OUT) 30 70 mV I = 1mA to 5mA 4
OUT Undervoltage Lockout 1 Rising VUVLO1 2.42 2.6 2.8 V Rising 4
OUT Undervoltage Lockout 1 Hysteresis ∆VUVH1 0.2 0.28 0.4 V 4
OUT Undervoltage Lockout 2 Rising VUVLO2 4.5 4.75 4.9 V Rising 4
OUT Undervoltage Lockout 2 Hysteresis ∆VUVH2 0.3 0.4 0.5 V 4
BASE Shunt Regulator Voltage (OUT, BASE) VZ(BASE) 5.5 6.1 6.6 V I = -10µA, OUT = 4.5V 4
BASE Shunt Regulator Load Regulation ∆VZ(BASE) 125 200 mV I = -10µA to -80µA, OUT = 4.5V 4
BASE Pin Leakage Current IBASE -0.1 -0.8 -5.5 µA OUT = 4.5V, BASE = -0.5V 4
VSS Pin Current, Regulation Amplifier On IVSS(AMP) -30 -45 -72 µA 4
VSS Pin Current, Charge Pump On IVSS(CP) -108 -160 -230 µA 4
External N-Channel Gate Drive (GATE, OUT) ∆VGATE 11.2 11.75 12.5 V OUT = 4.9V, I = 0, -1µA 4
GATE Pin Current, Start-Up (LTC4366C/I/H) IGATE(ST) -4.5 -7.5 -11 µA GATE = OUT = 0V 4
GATE Pin Current, Charge Pump On IGATE(CP) -14 -20 -28 µA GATE = 5V, OUT = 4.9V 4
GATE Pin Current, Fast Discharge IGATE(FD) 122 200 300 mA GATE = 10V, OUT = 4.9V 4
GATE Pin Current, Fault IGATE(FLT) 0.25 0.7 1.25 mA GATE = 10V, OUT = 4.9V 4
Regulation Threshold (OUT, FB) VFB(REG) 1.193 1.23 1.267 V 5
FB Pin Leakage Current IFB 0 1 µA OUT, FB = 1.2V 5
SD Pin Threshold Voltage (VDD, SD) Falling VSD(TH) 1 1.5 2.3 V Falling 5
SD Pin Hysteresis VSD(HYST) 129 260 530 mV 5
SD Pin Input Pull-Up Current ISD -0.5 -1.6 -3.5 µA VDD, SD = 0.7V 5
TIMER Pin Threshold VTIMER(H) 2.5 2.7 3.1 V TIMER Rising, VDD = 7V, OUT = VZ(OUT) 5
TIMER Pin Pull-Up Current (LTC4366C/I/H) ITIMER(UP) -5.1 -9 -13 µA TIMER = 1V 5
TIMER Pin Pull-Down Current ITIMER(DN) 0.7 1.8 2.8 µA TIMER = 1V 5
TIMER Pin Current Ratio ITIMER(RATIO) 15 20 25 % ITIMER(DN)/ITIMER(UP) 5
SD Low to Gate Low Filter Time Step tDLY, SD 420 700 1200 µs VDD, SD from 0V to 3V 5
FB Low to Gate Low Delay Time Step tDLY, FAST 60 150 300 ns OUT, FB from 0V to 1.3V 5
VDD Pin Current, Start-Up, Gate Low IVDD(STLO) 15 23 µA GATE = 0V, VDD = 7V, OUT = 0V 4
VDD Pin Current, Start-Up, Gate High IVDD(STHI) 8 13 µA GATE Open, VDD = 7V, OUT = 0V 4
VDD Pin Current, Shutdown IVDD(SD) 5 8 µA VDD = 7V, OUT = 0V 4
OUT Pin Current, Regulation Amplifier On IOUT(AMP) 37 54 µA 4
OUT Pin Current, Charge Pump On IOUT(CP) 150 220 µA 4
OUT Pin Current, Shutdown IOUT(SD) 3 6 µA 4
VSS Pin Current, Shutdown IVSS(SD) -7 -12 µA 4
Supply Voltage (VDD) VDD -0.3 10 V All voltages relative to VSS 2
Supply Voltage (OUT) OUT -0.3 5 V All voltages relative to VSS 2
Input Voltage FB FB -0.3 V OUT + 0.3V 2
Input Voltage TIMER TIMER -0.3 3.5 V All voltages relative to VSS 2
Input Voltage SD SD -0.3 10 V All voltages relative to VSS 2
Output Voltage BASE BASE -1.5 4 V All voltages relative to VSS 2
Output Voltage OUT, BASE OUT, BASE -0.3 5.5 V All voltages relative to VSS 2
Output Voltage GATE GATE -0.3 15 V Note 3 2
Output Voltage GATE, OUT GATE, OUT -0.3 10 V Note 3 2
IVDD Current IVDD 10 mA 2
IOUT Current IOUT 10 mA 2
BASE Current IBASE -300 10 µA 2
Operating Ambient Temperature Range (LTC4366C) TA 0 70 °C LTC4366C grade 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature (Soldering, 10 sec) 300 °C TSOT-23 Package Only 2
Maximum Junction Temperature TJMAX 150 °C TS8 package 2
Thermal Resistance, Junction to Ambient θJA 195 °C/W TS8 package 2

CAD (KiCad official)

  • Symbol: LTC4366CTS8-2#TRMPBF
  • Footprint: Package_TO_SOT_SMD:TSOT-23-8
  • 3D model: TSOT-23-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 e55569b484d5e348, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF