component
LTC4361IDC-2#TRMPBF
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LTC4361IDC-2#TRMPBF
Analog Devices · Pre-ordered Chips · DFN-8-EP(2x2)
LTC4361IDC-2#TRMPBF from Analog Devices, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ON | input | Active-low CMOS enable input with internal 5µA pull-down (-0.3V to 9V); high turns off GATE via a weak pull-down and enters a 1.5µA sleep mode, connect to ground or leave open if unused. |
| 2 | OUT | input | Output voltage sense input for the GATE-to-OUT clamp, connected to the source of the external N-channel MOSFET (-0.3V to 9V). |
| 3 | GATEP | output | Gate drive for optional external P-channel MOSFET for negative-voltage protection, clamped 5.8V below VIN with an internal 2M pull-down to ground; connect to IN if not used. |
| 4 | GND | power_in | Device ground. |
| 5 | IN | power_in | Supply voltage input (2.5V to 80V, absolute max 85V) with 5.8V overvoltage threshold and 5.7V recovery; GATE is held low during overvoltage lockout. |
| 6 | SENSE | input | Current sense input with a sense resistor between IN and SENSE; the MOSFET turns off when the drop exceeds 50mV for more than 10µs, tie to IN if overcurrent protection is not needed. |
| 7 | GATE | output | Gate drive for the external N-channel MOSFET with 10µA charge-pump pull-up, 3V/ms ramp limit and a clamp 6V above OUT; add an external capacitor to GND for a slower ramp. |
| 8 | PWRGD | output | Open-drain power good status output with internal 500k pull-up to OUT, pulls low 65ms after GATE exceeds VGATE(TH) and sinks up to 3mA. |
| 9 | EP | power_in | Exposed pad is ground; connection to PCB is optional. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-8-EP(2x2) |
| Category | Interface ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | 80 | V | 3 | ||
| Input Undervoltage Lockout | VIN(UVL) | 1.8 | 2.1 | 2.47 | V | VIN Rising | 3 |
| Input Supply Current | IIN | 220 | 400 | µA | VON = 0V | 3 | |
| Input Supply Current | IIN | 1.5 | 10 | µA | VON = 2.5V | 3 | |
| IN Pin Overvoltage Threshold | VIN(OV) | 5.684 | 5.8 | 5.916 | V | VIN Rising | 3 |
| IN Pin Overvoltage Recovery Threshold | VIN(OVL) | 5.51 | 5.7 | 5.85 | V | VIN Falling | 3 |
| Overvoltage Hysteresis | ΔVOV | 25 | 100 | 300 | mV | 3 | |
| Overcurrent Threshold | ΔVOC | 45 | 50 | 55 | mV | VIN, VSENSE | 3 |
| External N-Channel MOSFET Gate Drive (VGATE, VOUT) | ΔVGATE | 3.5 | 4.5 | 6 | V | 2.5V ≤ VIN < 3V, IGATE = -1µA | 3 |
| External N-Channel MOSFET Gate Drive (VGATE, VOUT) | ΔVGATE | 4.5 | 6 | 7.9 | V | 3V ≤ VIN < 5.5V, IGATE = -1µA | 3 |
| GATE High Threshold for PWRGD Status | VGATE(TH) | 5.7 | 6.3 | 6.8 | V | VIN = 3.3V | 3 |
| GATE High Threshold for PWRGD Status | VGATE(TH) | 6.7 | 7.2 | 7.8 | V | VIN = 5V | 3 |
| GATE Pull-Up Current | IGATE(UP) | -4.5 | -10 | -15 | µA | VGATE = 1V | 3 |
| GATE Ramp-Up | VGATE(UP) | 1.3 | 3 | 4.5 | V/ms | VGATE = 1V to 7V | 3 |
| GATE Pull-Down Current (Fast Turn-Off) | IGATE(FST) | 15 | 30 | 60 | mA | VIN = 6V, VGATE = 9V (C-, I-Grade) | 3 |
| GATE Pull-Down Current | IGATE(DN) | 5 | 40 | 80 | µA | VON = 2.5V, VGATE = 9V | 3 |
| SENSE Input Current | ISENSE(IN) | 10 | nA | VSENSE = 5V | 3 | ||
| OUT Input Current | IOUT(IN) | 5 | 10 | 20 | µA | VOUT = 5V, VON = 0V | 3 |
| OUT Input Current | IOUT(IN) | -3 | 0 | 3 | µA | VOUT = 5V, VON = 2.5V | 3 |
| ON Input Threshold | VON(TH) | 0.4 | 1.5 | V | 3 | ||
| ON Pull-Down Current | ION | 2 | 5 | 10 | µA | VON = 2.5V | 3 |
| IN to GATEP Clamp Voltage | VGATEP(CLP) | 5 | 5.8 | 7.9 | V | VIN = 8V to 80V | 3 |
| GATEP Resistive Pull-Down | RGATEP | 0.6 | 2 | 3.2 | MΩ | VGATEP = 3V | 3 |
| PWRGD Output Low Voltage | VPWRGD(OL) | 0.23 | 0.4 | V | VIN = 5V, IPWRGD = 3mA (C-, I-Grade) | 3 | |
| PWRGD Pull-Up Resistance to OUT | RPWRGD | 220 | 500 | 800 | kΩ | VIN = 6.5V, VPWRGD = 1V | 3 |
| GATE On Delay | tON | 50 | 130 | 219 | ms | VIN High to IGATE = -5µA | 3 |
| GATE Off Propagation Delay | tOFF | 5 | 10 | µs | VIN = Step 5V to 6.5V to PWRGD High | 3 | |
| GATE Off Propagation Delay | tOFF | 0.25 | 1 | µs | VIN, VSENSE = Step 0mV to 100mV | 3 | |
| PWRGD Delay | tPWRGD | 25 | 65 | 105 | µs | VIN = Step 5V to 6.5V | 3 |
| PWRGD Delay | tPWRGD | 0.25 | 1 | ms | VGATE > VGATE(TH) to PWRGD Low | 3 | |
| ON High to GATE Off | tON(OFF) | 2 | 5 | µs | VON = Step 0V to 2.5V | 3 | |
| Bias Supply Voltage (IN) | IN | -0.3 | 85 | V | 2 | ||
| SENSE Input Voltage | SENSE | -0.3 | 85 | V | 2 | ||
| OUT, ON Input Voltage | OUT, ON | -0.3 | 9 | V | 2 | ||
| PWRGD Output Voltage | PWRGD | -0.3 | 9 | V | 2 | ||
| GATE Output Voltage | GATE | -0.3 | 15 | V | Note 3 | 2 | |
| GATEP Output Voltage | GATEP | -0.3 | 85 | V | 2 | ||
| IN to GATEP | -0.3 | 10 | V | 2 | |||
| Operating Temperature Range (LTC4361I) | -40 | 85 | °C | I-grade | 2 | ||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Maximum Junction Temperature | TJMAX | 125 | °C | DC package | 2 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 102 | °C/W | DC package, 8-lead 2mm × 2mm DFN | 2 |
CAD (KiCad official)
- Symbol:
LTC4361IDC-2#TRMPBF - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.45mm_EP0.64x1.37mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
ltc4361idc-2-trmpbf-etched.step/ltc4361idc-2-trmpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc4361idc-2-trmpbf.step/ltc4361idc-2-trmpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
9b84eb4e36b68de9, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTC4361IDC-2#TRMPBF
**Analog Devices** · Pre-ordered Chips · DFN-8-EP(2x2)
LTC4361IDC-2#TRMPBF from Analog Devices, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ON | input | Active-low CMOS enable input with internal 5µA pull-down (-0.3V to 9V); high turns off GATE via a weak pull-down and enters a 1.5µA sleep mode, connect to ground or leave open if unused. |
| 2 | OUT | input | Output voltage sense input for the GATE-to-OUT clamp, connected to the source of the external N-channel MOSFET (-0.3V to 9V). |
| 3 | GATEP | output | Gate drive for optional external P-channel MOSFET for negative-voltage protection, clamped 5.8V below VIN with an internal 2M pull-down to ground; connect to IN if not used. |
| 4 | GND | power_in | Device ground. |
| 5 | IN | power_in | Supply voltage input (2.5V to 80V, absolute max 85V) with 5.8V overvoltage threshold and 5.7V recovery; GATE is held low during overvoltage lockout. |
| 6 | SENSE | input | Current sense input with a sense resistor between IN and SENSE; the MOSFET turns off when the drop exceeds 50mV for more than 10µs, tie to IN if overcurrent protection is not needed. |
| 7 | GATE | output | Gate drive for the external N-channel MOSFET with 10µA charge-pump pull-up, 3V/ms ramp limit and a clamp 6V above OUT; add an external capacitor to GND for a slower ramp. |
| 8 | PWRGD | output | Open-drain power good status output with internal 500k pull-up to OUT, pulls low 65ms after GATE exceeds VGATE(TH) and sinks up to 3mA. |
| 9 | EP | power_in | Exposed pad is ground; connection to PCB is optional. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-8-EP(2x2) |
| Category | Interface ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | | 80 | V | | 3 |
| Input Undervoltage Lockout | VIN(UVL) | 1.8 | 2.1 | 2.47 | V | VIN Rising | 3 |
| Input Supply Current | IIN | | 220 | 400 | µA | VON = 0V | 3 |
| Input Supply Current | IIN | | 1.5 | 10 | µA | VON = 2.5V | 3 |
| IN Pin Overvoltage Threshold | VIN(OV) | 5.684 | 5.8 | 5.916 | V | VIN Rising | 3 |
| IN Pin Overvoltage Recovery Threshold | VIN(OVL) | 5.51 | 5.7 | 5.85 | V | VIN Falling | 3 |
| Overvoltage Hysteresis | ΔVOV | 25 | 100 | 300 | mV | | 3 |
| Overcurrent Threshold | ΔVOC | 45 | 50 | 55 | mV | VIN, VSENSE | 3 |
| External N-Channel MOSFET Gate Drive (VGATE, VOUT) | ΔVGATE | 3.5 | 4.5 | 6 | V | 2.5V ≤ VIN < 3V, IGATE = -1µA | 3 |
| External N-Channel MOSFET Gate Drive (VGATE, VOUT) | ΔVGATE | 4.5 | 6 | 7.9 | V | 3V ≤ VIN < 5.5V, IGATE = -1µA | 3 |
| GATE High Threshold for PWRGD Status | VGATE(TH) | 5.7 | 6.3 | 6.8 | V | VIN = 3.3V | 3 |
| GATE High Threshold for PWRGD Status | VGATE(TH) | 6.7 | 7.2 | 7.8 | V | VIN = 5V | 3 |
| GATE Pull-Up Current | IGATE(UP) | -4.5 | -10 | -15 | µA | VGATE = 1V | 3 |
| GATE Ramp-Up | VGATE(UP) | 1.3 | 3 | 4.5 | V/ms | VGATE = 1V to 7V | 3 |
| GATE Pull-Down Current (Fast Turn-Off) | IGATE(FST) | 15 | 30 | 60 | mA | VIN = 6V, VGATE = 9V (C-, I-Grade) | 3 |
| GATE Pull-Down Current | IGATE(DN) | 5 | 40 | 80 | µA | VON = 2.5V, VGATE = 9V | 3 |
| SENSE Input Current | ISENSE(IN) | | | 10 | nA | VSENSE = 5V | 3 |
| OUT Input Current | IOUT(IN) | 5 | 10 | 20 | µA | VOUT = 5V, VON = 0V | 3 |
| OUT Input Current | IOUT(IN) | -3 | 0 | 3 | µA | VOUT = 5V, VON = 2.5V | 3 |
| ON Input Threshold | VON(TH) | 0.4 | | 1.5 | V | | 3 |
| ON Pull-Down Current | ION | 2 | 5 | 10 | µA | VON = 2.5V | 3 |
| IN to GATEP Clamp Voltage | VGATEP(CLP) | 5 | 5.8 | 7.9 | V | VIN = 8V to 80V | 3 |
| GATEP Resistive Pull-Down | RGATEP | 0.6 | 2 | 3.2 | MΩ | VGATEP = 3V | 3 |
| PWRGD Output Low Voltage | VPWRGD(OL) | | 0.23 | 0.4 | V | VIN = 5V, IPWRGD = 3mA (C-, I-Grade) | 3 |
| PWRGD Pull-Up Resistance to OUT | RPWRGD | 220 | 500 | 800 | kΩ | VIN = 6.5V, VPWRGD = 1V | 3 |
| GATE On Delay | tON | 50 | 130 | 219 | ms | VIN High to IGATE = -5µA | 3 |
| GATE Off Propagation Delay | tOFF | | 5 | 10 | µs | VIN = Step 5V to 6.5V to PWRGD High | 3 |
| GATE Off Propagation Delay | tOFF | | 0.25 | 1 | µs | VIN, VSENSE = Step 0mV to 100mV | 3 |
| PWRGD Delay | tPWRGD | 25 | 65 | 105 | µs | VIN = Step 5V to 6.5V | 3 |
| PWRGD Delay | tPWRGD | | 0.25 | 1 | ms | VGATE > VGATE(TH) to PWRGD Low | 3 |
| ON High to GATE Off | tON(OFF) | | 2 | 5 | µs | VON = Step 0V to 2.5V | 3 |
| Bias Supply Voltage (IN) | IN | -0.3 | | 85 | V | | 2 |
| SENSE Input Voltage | SENSE | -0.3 | | 85 | V | | 2 |
| OUT, ON Input Voltage | OUT, ON | -0.3 | | 9 | V | | 2 |
| PWRGD Output Voltage | PWRGD | -0.3 | | 9 | V | | 2 |
| GATE Output Voltage | GATE | -0.3 | | 15 | V | Note 3 | 2 |
| GATEP Output Voltage | GATEP | -0.3 | | 85 | V | | 2 |
| IN to GATEP | | -0.3 | | 10 | V | | 2 |
| Operating Temperature Range (LTC4361I) | | -40 | | 85 | °C | I-grade | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Maximum Junction Temperature | TJMAX | | | 125 | °C | DC package | 2 |
| Junction-to-Ambient Thermal Resistance | θJA | | 102 | | °C/W | DC package, 8-lead 2mm × 2mm DFN | 2 |
## CAD (KiCad official)
- Symbol: `LTC4361IDC-2#TRMPBF`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.45mm_EP0.64x1.37mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `ltc4361idc-2-trmpbf-etched.step` / `ltc4361idc-2-trmpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc4361idc-2-trmpbf.step` / `ltc4361idc-2-trmpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/LTC4361-1-4361-2.pdf) (16 pp, sha256 `9b84eb4e36b68de9`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltc4361idc-2-trmpbf-datasheet.pdf)