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LTC4217CDHC#TRPBF
Public Made by Adomby adom
Analog Devices Surge Suppressors, DFN-16-EP(3x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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LTC4217CDHC#TRPBF
Analog Devices · Surge Suppressors · DFN-16-EP(3x5)
LTC4217CDHC#TRPBF from Analog Devices, in a DFN-16-EP(3x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage and current sense input with a 2.9V to 26.5V operating range and a 2.73V undervoltage lockout threshold. |
| 2 | UV | input | Undervoltage comparator input; the switch turns off when UV falls below 1.15V, and pulling it below 0.62V resets an overcurrent fault. Tie high if unused. |
| 3 | OV | input | Overvoltage comparator input; the switch turns off when OV rises above 1.235V. Tie to GND if unused. |
| 4 | TIMER | passive | Timer input; a capacitor to ground sets a 12ms/µF current-limit duration before the switch turns off, and tying it to INTVCC gives a fixed 2ms overcurrent delay and 100ms auto-retry. |
| 5 | INTVCC | power_out | Internal 3.1V supply decoupling output that must have a 1µF or larger bypass capacitor and must not be overloaded. |
| 6 | GND | power_in | Device ground. |
| 7 | OUT | passive | Output of the internal MOSFET switch, connected directly to the load. |
| 8 | OUT | passive | Output of the internal MOSFET switch, connected directly to the load. |
| 9 | OUT | passive | Output of the internal MOSFET switch, connected directly to the load. |
| 10 | GATE | output | Gate drive for the internal N-channel MOSFET, with a 24µA pull-up, a 0.3V/ms start-up ramp, a 250µA pull-down during UV/OV faults, and a 140mA fast pull-down during short-circuit or UVLO. |
| 11 | PG | output | Open-drain power good output that pulls low when FB falls below 1.21V and releases high when FB rises above 1.23V and GATE-to-OUT exceeds 4.2V. |
| 12 | FLT | output | Open-drain overcurrent fault output that pulls low when the circuit breaker trips; tie to UV for overcurrent auto-retry. |
| 13 | FB | input | Foldback and power good input; below 0.6V the current limit is reduced by foldback, and below 1.21V the PG pin pulls low. |
| 14 | IMON | output | Current monitor output sourcing the MOSFET current divided by 20,000; a 20k resistor to GND gives 0V to 2V for 0A to 2A. |
| 15 | ISET | output | Current limit adjustment pin; leave open for a 2A limit, and RSET to ground should not be less than 2k. |
| 16 | VDD | power_in | Supply voltage and current sense input with a 2.9V to 26.5V operating range and a 2.73V undervoltage lockout threshold. |
| 17 | SENSE | passive | Exposed pad and current sense node / MOSFET drain that limits the VDD-to-SENSE voltage to 15mV (2A) or less and must be soldered to an electrically isolated PCB trace for heat transfer. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-16-EP(3x5) |
| Category | TVS/Fuse/Board Level Protection |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | -0.3 | 28 | V | 2 | ||
| Input Voltages FB, OV, UV | -0.3 | 12 | V | 2 | |||
| Input Voltage TIMER | -0.3 | 3.5 | V | 2 | |||
| Output Voltages PG, FLT | -0.3 | 35 | V | 2 | |||
| Output Voltages ISET, IMON | -0.3 | 3 | V | 2 | |||
| Output Voltage INTVCC | -0.3 | 3.5 | V | 2 | |||
| Output Voltage GATE | -0.3 | 33 | V | Note 3 | 2 | ||
| Junction Temperature | 125 | °C | Notes 4, 5 | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Operating Ambient Temperature Range LTC4217C | 0 | 70 | °C | C-grade | 2 | ||
| VDD Input Supply Range | VDD | 2.9 | 26.5 | V | 3 | ||
| IDD Input Supply Current | IDD | 1.6 | 3 | mA | MOSFET On, No Load | 3 | |
| Input Supply Undervoltage Lockout | VDD(UVL) | 2.65 | 2.73 | 2.85 | V | VDD Rising | 3 |
| Current Limit Threshold | ILIM(TH) | 1.9 | 2 | 2.1 | A | VFB = 1.23V | 3 |
| Current Limit Threshold (full temperature range) | ILIM(TH) | 1.85 | 2 | 2.15 | A | VFB = 1.23V | 3 |
| Current Limit Threshold foldback | ILIM(TH) | 0.35 | 0.5 | 0.7 | A | VFB = 0V | 3 |
| Current Limit Threshold with RSET | ILIM(TH) | 0.85 | 1 | 1.17 | A | VFB = 1.23V, RSET = 20kΩ | 3 |
| MOSFET + Sense Resistor On-Resistance | RON | 15 | 33 | 50 | mΩ | C-Grade, I-Grade | 3 |
| GATE Pin Turn-On Ramp Rate | dVGATE/dt | 0.15 | 0.3 | 0.55 | V/ms | 3 | |
| OV, UV, FB Input Current | IIN | -1 | 0 | 1 | µA | V = 1.2V, LTC4217 | 4 |
| OV, UV, FB Threshold Voltage | VTH | 1.21 | 1.235 | 1.26 | V | VPIN Rising | 4 |
| OV Hysteresis | ΔVOV(HYST) | 10 | 20 | 30 | mV | 4 | |
| UV Hysteresis | ΔVUV(HYST) | 50 | 80 | 110 | mV | 4 | |
| UV Reset Threshold Voltage | VUV(RTH) | 0.55 | 0.62 | 0.7 | V | VUV Falling | 4 |
| FB Power Good Hysteresis | ΔVFB(HYST) | 10 | 20 | 30 | mV | 4 | |
| ISET Internal Resistor | RISET | 19 | 20 | 21 | kΩ | 4 | |
| PG, FLT Input Leakage Current | IOH | -10 | 0 | 10 | µA | 30V | 4 |
| TIMER Pin High Threshold | VTIMER(H) | 1.2 | 1.235 | 1.28 | V | VTIMER Rising | 4 |
| TIMER Pin Low Threshold | VTIMER(L) | 0.1 | 0.21 | 0.3 | V | VTIMER Falling | 4 |
| TIMER Pin Pull-Up Current | ITIMER(UP) | -120 | -100 | -80 | µA | VTIMER = 0V | 4 |
| TIMER Pin Pull-Down Current | ITIMER(DN) | 1.4 | 2 | 2.6 | µA | VTIMER = 1.2V | 4 |
| TIMER Pin Current Ratio | ITIMER(RATIO) | 1.6 | 2 | 2.7 | % | ITIMER(DN)/ITIMER(UP) | 4 |
| IMON Pin Current Gain | AIMON | 47.5 | 50 | 52.5 | µA/A | IOUT = 2A | 4 |
| IMON Pin Offset Current | IOFF(IMON) | -7.5 | 0 | 7.5 | µA | IOUT = 132mA | 4 |
| Gate Pull-Up Current | IGATE(UP) | -29 | -24 | -19 | µA | Gate Drive On, VGATE = VOUT = 12V | 4 |
| Gate Pull-Down Current | IGATE(DN) | 190 | 250 | 400 | µA | Gate Drive Off, VGATE = 18V, VOUT = 12V; C-Grade, I-Grade | 4 |
| Input High (OV), Input Low (UV) to Gate Low Propagation Delay | tPHL(GATE) | 8 | 10 | µs | VGATE < 16.5V Falling | 4 | |
| Short-Circuit to Gate Low Propagation Delay | tPHL(ILIM) | 1 | 5 | µs | VFB = 0, Step ISENSE to 1.2A, VGATE < 16.5V Falling | 4 | |
| Turn-On Delay | tD(ON) | 50 | 100 | 150 | ms | Step VUV to 2V, VGATE > 13V | 4 |
| Circuit Breaker Filter Delay Time (Internal) | tD(CB) | 1.5 | 2 | 2.7 | ms | VFB = 0V, Step ISENSE to 1.2A; C-Grade, I-Grade | 4 |
| Auto-Retry Turn-On Delay (Internal) | tD(AUTO-RETRY) | 50 | 100 | 150 | ms | 4 | |
| Thermal Resistance, junction to ambient (exposed pad soldered) | θJA | 43 | °C/W | DHC 16-lead DFN, exposed pad soldered | 2 | ||
| Thermal Resistance, junction to ambient (exposed pad not soldered) | θJA | 140 | °C/W | DHC 16-lead DFN, exposed pad not soldered | 2 |
CAD (KiCad official)
- Symbol:
LTC4217CDHC#TRPBF - Footprint:
Package_DFN_QFN:DFN-16-1EP_3x5mm_P0.5mm_EP1.66x4.4mm - 3D model: DFN-16-EP(3x5) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
ec0c241caa1e59bf, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).