component
LTC4162EUFD-FSTM#PBF
Public Made by Adomby adom
Analog Devices Battery Management, QFN-28(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownLTC4162EUFD-FSTM#PBF
Analog Devices · Battery Management · QFN-28(4x5)
LTC4162EUFD-FSTM#PBF from Analog Devices, in a QFN-28(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOST | power_out | Gate-drive bias for the high-side switch, pumped relative to SW and charged from INTVCC through an internal diode; requires a 22nF multilayer ceramic capacitor from SW to BOOST. |
| 2 | INTVCC | power_out | Bypass pin for the internal 5V regulator that powers the analog circuitry; requires a 4.7µF multilayer ceramic capacitor to GND. |
| 3 | VOUTA | power_out | Analog system power pin that powers the majority of internal circuits; requires a 0.1µF multilayer ceramic capacitor to GND. |
| 4 | CLN | input | Negative terminal connection of the sense resistor that measures and regulates input current by limiting charge current. |
| 5 | CLP | input | Positive terminal connection of the sense resistor that measures and regulates input current by limiting charge current. |
| 6 | INFET | output | Gate control output for an input reverse-blocking external N-channel MOSFET between VIN and VOUT. |
| 7 | VIN | power_in | Supply voltage detection and INFET charge-pump supply for the PowerPath; requires a 0.1µF multilayer ceramic capacitor to GND. |
| 8 | VCC2P5 | power_out | Bypass pin for the internal 2.5V regulator that powers the internal logic; requires a 1µF multilayer ceramic capacitor to GND. |
| 9 | NTCBIAS | power_out | NTC thermistor bias output that applies 1.2V during NTC measurement; connect a low-temperature-coefficient bias resistor equal to the thermistor nominal value between NTCBIAS and NTC. |
| 10 | NTC | input | Thermistor input digitized to qualify battery charging and readable over I2C; requires a low-drift bias resistor from NTCBIAS and a thermistor to ground. |
| 11 | RT | passive | Switching regulator frequency control pin; a resistor from RT to GND sets the internal oscillator frequency (fOSC 1.4 to 1.6MHz at RT = 63.4k). |
| 12 | SMBALERT | output | Open-drain interrupt output that pulls low when one or more programmable alerts is triggered. |
| 13 | SCL | input | Open-drain clock input for the I2C port, with input levels scaled with respect to DVCC. |
| 14 | SDA | bidirectional | Open-drain data input/output for the I2C port, with input levels scaled with respect to DVCC. |
| 15 | DVCC | power_in | Logic supply for the I2C port that sets the SDA and SCL reference levels; the logic reference range is 1.8V to 5.5V. |
| 16 | SYNC | input | Optional external clock input that the switching charger locks to, near the RT-programmed frequency; ground if the feature is not used. |
| 17 | CELLS0 | input | Cell-count selection strap used with CELLS1; must be tied to INTVCC, VCC2P5 or GND (see Table 5). |
| 18 | CELLS1 | input | Cell-count selection strap used with CELLS0; must be tied to INTVCC, VCC2P5 or GND (see Table 5). |
| 19 | BATSENS+ | input | Positive battery terminal sense pin that should be Kelvin-sensed; requires a 10µF multilayer ceramic capacitor to ground. |
| 20 | CSN | input | Negative terminal connection of the current sense resistor used to measure and limit charge current. |
| 21 | CSP | input | Positive terminal connection of the current sense resistor used to measure and limit charge current. |
| 22 | BATFET | output | Gate control pin for a reverse-blocking external N-channel MOSFET between the battery and VOUT. |
| 23 | PGND | power_in | Power ground pin that should connect to a copper pour forming the return for the VOUT bypass capacitor. |
| 24 | PGND | power_in | Power ground pin that should connect to a copper pour forming the return for the VOUT bypass capacitor. |
| 25 | SW | output | Switching regulator power transmission pin that delivers power from VOUT to the battery; the inductor connects from SW to the sense resistor at CSP. |
| 26 | SW | output | Switching regulator power transmission pin that delivers power from VOUT to the battery; the inductor connects from SW to the sense resistor at CSP. |
| 27 | VOUT | power_in | Switching regulator input pin that delivers power to the switching charger; bypassing these pins takes precedence over other layout considerations, with 10µF a good starting point. |
| 28 | VOUT | power_in | Switching regulator input pin that delivers power to the switching charger; bypassing these pins takes precedence over other layout considerations, with 10µF a good starting point. |
| 29 | AGND | power_in | Exposed pad analog ground that returns all analog circuitry; must be soldered to the PCB and connected to an analog ground pour common with PGND (pins 23 and 24). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-28(4x5) |
| Category | Power Management (PMIC) |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Battery and input supply pins absolute maximum (BATSENS+, VIN, CSP, CSN, CLP, CLN, VOUT, VOUTA) | BATSENS+, VIN, CSP, CSN, CLP, CLN, VOUT, VOUTA | -0.3 | 36 | V | 3 | ||
| Sense pin differential absolute maximum (CSP to CSN, CLP to CLN) | -0.3 | 0.3 | V | 3 | |||
| Logic pin absolute maximum (CELLSO, CELLS1, SYNC) | CELLSO, CELLS1, SYNC | -0.3 | V | 3 | |||
| DVCC absolute maximum | DVCC | -0.3 | 5.5 | V | 3 | ||
| I2C pin absolute maximum (SDA, SCL, SMBALERT) | SDA, SCL, SMBALERT | -0.3 | V | 3 | |||
| Switch pin current absolute maximum | ISW | -3.5 | 3.5 | A | 3 | ||
| Operating junction temperature range | -40 | 125 | °C | Notes 2, 4 | 3 | ||
| Storage temperature range | -65 | 150 | °C | 3 | |||
| Electrical: input supply voltage | VIN | 4.5 | 35 | V | l: over full operating junction temperature range | 4 | |
| Electrical: battery voltage | VBAT | 2.7 | 35 | V | l: over full operating junction temperature range | 4 | |
| Battery drain current, terminated | IBATSENS+ | 0.5 | 1 | µA | VIN, VBATSENS+ > VIN_DUVLO, Terminated | 4 | |
| Battery drain current, input below UVLO | IBATSENS+ | 54 | 100 | µA | VIN, VBATSENS+ < VIN_DUVLO | 4 | |
| Battery drain current, ship mode | IBATSENS+ | 2.8 | 5 | µA | VIN = 0, SHIPMODE Activated | 4 | |
| VIN drain current, terminated | IVIN | 115 | 200 | µA | VIN, VBATSENS+ > VIN_DUVLO, Terminated | 4 | |
| Charge voltage range | VCHARGE | 3.4125 | 3.8 | V | 4 | ||
| Charge voltage accuracy | VCHARGE | -0.5 | 0.5 | % | Per cell_count | 4 | |
| Charge voltage accuracy (l) | VCHARGE | -1.5 | 1.5 | % | Per cell_count; l | 4 | |
| Charge servo voltage range (VCSP, VCSN) | ICHARGE | 1 | 32 | mV | ICHARGE = (VCSP, VCSN)/RSNSB; Note 5 | 4 | |
| Charge current servo accuracy | ICHARGE | -0.25 | 0.25 | mV | 4 | ||
| Charge current servo accuracy (l) | ICHARGE | -0.75 | 0.75 | mV | l | 4 | |
| Input current servo voltage range (VCLP, VCLN) | IINLIM | 0.5 | 32 | mV | IIN = (VCLP, VCLN)/RSNSI; Note 6 | 4 | |
| Input current servo accuracy | IINLIM | -0.2 | 0.2 | mV | 4 | ||
| Input voltage limit (VINLIM) range | VINLIM | 0.14 | 36 | V | 4 | ||
| VINLIM full scale accuracy | VINLIM | -1 | 1 | % | 4 | ||
| Switching frequency | fOSC | 1.4 | 1.5 | 1.6 | MHz | RT = 63.4k; l | 5 |
| Maximum duty cycle | DMAX | 99.5 | % | 5 | |||
| VIN charger enable undervoltage lockout rising threshold | VIN_UVLO | 4.2 | 4.4 | 4.6 | V | Rising Threshold | 5 |
| VIN to BATSENS+ charger enable differential UVLO rising threshold | VIN_DUVLO | 100 | 150 | 200 | mV | Rising Threshold | 5 |
| VIN charger disable overvoltage lockout rising threshold | VIN_OVLO | 37.6 | 38.6 | 40 | V | Rising Threshold | 5 |
| INTVCC telemetry enable undervoltage lockout rising threshold | VINTVCC_UVLO | 2.75 | 2.85 | 2.95 | V | Rising Threshold | 5 |
| IBAT telemetry offset error | IBAT | -0.15 | 0.15 | mV | IBAT = (VCSP, VCSN)/RSNSB; 0.32mV < VCSP, VCSN < 32mV | 5 | |
| IBAT telemetry span error | IBAT | -1 | 1 | %rdng | IBAT = (VCSP, VCSN)/RSNSB; 0.32mV < VCSP, VCSN < 32mV | 5 | |
| IIN telemetry offset error | IIN | -0.15 | 0.15 | mV | IIN = (VCLP, VCLN)/RSNSI; 0.32mV < VCLP, VCLN < 32mV | 5 | |
| IIN telemetry span error | IIN | -1 | 1 | %rdng | IIN = (VCLP, VCLN)/RSNSI; 0.32mV < VCLP, VCLN < 32mV | 5 | |
| VIN telemetry offset error | VIN | -25 | 25 | mV | 3V < VIN < 35V | 5 | |
| VIN telemetry span error | VIN | -1 | 1 | %rdng | 3V < VIN < 35V | 5 | |
| VBATSENS+ telemetry offset error (per cell_count) | VBATSENS+ | -10 | 10 | mV | 2V < VBATSENS+ < 3.8V | 5 | |
| VBATSENS+ telemetry span error (per cell_count) | VBATSENS+ | -1 | 1 | %rdng | 2V < VBATSENS+ < 3.8V | 5 | |
| VOUT telemetry offset error | VOUT | -25 | 25 | mV | 3V < VOUT < 35V | 5 | |
| VOUT telemetry span error | VOUT | -1 | 1 | %rdng | 3V < VOUT < 35V | 5 | |
| VNTC/VNTCBIAS telemetry offset error | VNTC/VNTCBIAS | -1 | 1 | mV/V | 0 < VNTC/VNTCBIAS < 1 | 5 | |
| VNTC/VNTCBIAS telemetry span error | VNTC/VNTCBIAS | -1 | 1 | %rdng | 0 < VNTC/VNTCBIAS < 1 | 5 | |
| DVCC logic reference level | DVCC | 1.8 | 5.5 | V | l | 5 | |
| I2C input high threshold | VIHI2C | 70 | % DVCC | 5 | |||
| I2C input low threshold | VILI2C | 30 | % DVCC | 5 | |||
| Digital output low (SDA/SMBALERT) | VOLI2C | 400 | mV | ISDA/SMBALERT = 3mA | 5 | ||
| SCL clock frequency | FSCL | 400 | kHz | 5 | |||
| LOW period of SCL clock | tLOW | 1.3 | µs | 6 | |||
| HIGH period of SCL clock | tHIGH | 0.6 | µs | 6 | |||
| Bus free time between start and stop conditions | tBUF | 1.3 | µs | 6 | |||
| Hold time after (repeated) start condition | tHD,STA | 0.6 | µs | 6 | |||
| Stop condition set-up time | tSU,STO | 0.6 | µs | 6 | |||
| Output data hold time | tHD,DAT(OUT) | 0 | 900 | ns | 6 | ||
| Data set-up time | tSU,DAT | 100 | ns | 6 | |||
| SYNC input high threshold | VIHSYNC | 1.5 | V | l | 6 | ||
| SYNC input low threshold | VILSYNC | 0.2 | V | l | 6 | ||
| Pin leakage current (NTC, CELLS0, CELLS1, SDA, SCL, SYNC, SMBALERT) | -50 | 50 | nA | 6 | |||
| Thermal: maximum junction temperature | TJMAX | 125 | °C | 3 | |||
| Thermal resistance, junction to ambient | θJA | 43 | °C/W | 3 | |||
| Thermal resistance, junction to case | θJC | 3.4 | °C/W | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | PGND (Pins 23,24): Power ground pins. These pins should be connected to a copper pour that forms the return for | 11 |
CAD (KiCad official)
- Symbol:
LTC4162EUFD-FSTM#PBF - Footprint:
Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: QFN-28(4x5) (KiCad packages3D, STEP)
- 3D model files:
ltc4162eufd-fstm-pbf-etched.step/ltc4162eufd-fstm-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc4162eufd-fstm-pbf.step/ltc4162eufd-fstm-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (52 pp, sha256
6aecc6c02aff81b7, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).