component
LTC4041EUFD#PBF
Public Made by Adomby adom
Analog Devices Battery Management, QFN-24-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LTC4041EUFD#PBF
Analog Devices · Battery Management · QFN-24-EP(4x5)
LTC4041EUFD#PBF from Analog Devices, in a QFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSYS | power_out | System voltage output that supplies the external load from the input or from the supercapacitor in backup, and must be bypassed with at least 100µF of low-ESR ceramic capacitor to GND. |
| 2 | PROG | passive | Charge-current program pin where an external resistor to GND sets full-scale charge current, with PROG servoing to 0.8V and an SCAP-to-PROG current ratio of 2500. |
| 3 | IMON | output | VSYS current monitor whose voltage is 32 times the VIN-to-CLN differential voltage, and charge current is reduced when IMON reaches 0.8V. |
| 4 | CHGEN | input | Disable input for the supercapacitor charger that enables charging when tied to GND and disables it when above 1.2V, and must not be left unconnected. |
| 5 | BSTEN | input | Disable input for the backup boost converter that enables backup when tied to GND and disables it when above 1.2V, and must not be left unconnected. |
| 6 | VIN | power_in | Input pin that can be driven directly when OVP is not used, or fed through an external N-channel FET from the input supply VPWR when OVP is required. |
| 7 | CLN | input | Negative terminal of the external input-current sense resistor between VIN and CLN, where the charger regulates to 25mV across the resistor but does not limit system current if the drop exceeds 25mV. |
| 8 | CAPFLT | output | Open-drain supercapacitor fault output that pulls low and disables charging if any single supercapacitor exceeds 2.7V or disables backup if any falls below -20mV, with a 10µA pull-down capability and tie-high to keep operation enabled. |
| 9 | BAL | passive | Supercapacitor balance point for a two-capacitor stack that the internal balancer drives to half of VSCAP, and which must be left open when only one supercapacitor is used. |
| 10 | RSTFB | input | High-impedance input to the SYSGD comparator with a 0.74V falling threshold and 20mV hysteresis, driven from an external divider between VSYS and GND. |
| 11 | SYSGD | output | Open-drain system power-good output that is pulled to GND by an internal N-channel MOSFET whenever RSTFB falls below 0.74V. |
| 12 | CAPFB | input | Supercapacitor (single or two-stack) feedback input from an external divider between SCAP and GND that nominally servos to 0.8V to program the final charge voltage. |
| 13 | CAPGD | output | Open-drain supercapacitor power-good output that stays pulled low until CAPFB rises to 92.5% of its regulation point. |
| 14 | PFO | output | Open-drain power-fail status output that is pulled to GND when PFI is below its falling threshold and becomes high impedance once PFI rises above its rising threshold. |
| 15 | IGATE | output | Gate drive for the external N-channel pass FET(s) from an internal charge pump, where the mandatory VIN-to-VSYS FET disconnects the system from the input during backup. |
| 16 | OVSNS | input | Overvoltage protection sense input that connects through a 6.2k resistor to the input supply and the pass FET drain, or is shorted to VIN if OVP is unused, and pulls IGATE to GND when it exceeds 6V (typical). |
| 17 | CPF | passive | Minimum backup time program pin where a capacitor sets tMIN-BACKUP, and which must not be tied to GND or left unconnected. |
| 18 | BSTFB | input | Feedback input for the backup boost regulator that servos to 0.8V during backup operation. |
| 19 | PFI | input | High-impedance power-fail input with a 1.19V falling threshold and 40mV hysteresis that controls PFO and sets the input voltage below which backup boost starts. |
| 20 | CAPSEL | input | Supercapacitor stack selector that must be tied above 1.2V for a two-capacitor stack or to GND for a single supercapacitor, and must not be left unconnected. |
| 21 | SW | passive | Switch pin for the buck charger and boost backup converter, connected to SCAP through a 1µH to 2.2µH inductor. |
| 22 | SW | passive | Switch pin for the buck charger and boost backup converter, connected to SCAP through a 1µH to 2.2µH inductor. |
| 23 | SCAP | bidirectional | Supercapacitor pin for a single supercapacitor or the top of a two-capacitor stack, which supplies VSYS through the boost in backup or is charged from VSYS by the buck charger. |
| 24 | VSYS | power_out | System voltage output pin that supplies the external load from the input or from the supercapacitor in backup, and must be bypassed with at least 100µF of low-ESR ceramic capacitor to GND. |
| 25 | GND | power_in | Exposed pad that must be soldered to the PCB to provide low electrical and thermal impedance ground, with a continuous ground plane on the second layer strongly recommended. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-24-EP(4x5) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Transient Voltage | VIN | -0.3 | 7 | V | t < 1ms, Duty Cycle < 1% | 2 | |
| Steady-State Voltage (VIN, SCAP, BAL, CLN, VSYS, BSTFB, PFI, CPF, CAPFB, CAPFLT, PFO, SYSGD, OVSNS, IMON) | VIN, SCAP, BAL, CLN, VSYS, BSTFB, PFI, CPF, CAPFB, CAPFLT, PFO, SYSGD, OVSNS, IMON | -0.3 | 6 | V | Steady state | 2 | |
| Voltage (BSTEN, CHGEN, CAPGD, RSTFB, CAPSEL) | BSTEN, CHGEN, CAPGD, RSTFB, CAPSEL | -0.3 | V | Upper limit is [Max (VIN, VSCAP, VSYS) +0.3V]; no numeric max printed | 2 | ||
| IOVSNS Current | IOVSNS | -10 | 10 | mA | 2 | ||
| Current (ICAPGD, IPFO, ISYSGD) | ICAPGD, IPFO, ISYSGD | 10 | mA | 2 | |||
| IPROG Current | IPROG | -1.1 | mA | 2 | |||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | Notes 2, 3 | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | Note 1 | 2 | |
| Maximum Junction Temperature | TJMAX | 125 | °C | 2 | |||
| Input Voltage Range | VIN | 2.9 | 5.5 | V | l | 3 | |
| Supercapacitor Voltage Range (Backup Boost Input) | VSCAP | 5.4 | V | l | 3 | ||
| VIN and VSYS Total Quiescent Current, Charger Mode with Charging Complete and Backup Boost Active | 800 | 1600 | µA | CAPSEL = 1 | 3 | ||
| SCAP Quiescent Current, Charger Mode with Charging Complete and Backup Boost Active | 13 | 26 | µA | CAPSEL = 1 | 3 | ||
| VIN and VSYS Total Quiescent Current, Charger Mode with Charging Complete and Backup Boost in Sleep | 275 | 550 | µA | CAPSEL = 1 | 3 | ||
| SCAP Quiescent Current, Charger Mode with Charging Complete and Backup Boost in Sleep | 13 | 26 | µA | CAPSEL = 1 | 3 | ||
| VSYS Quiescent Current, Backup Mode with Backup Boost in Sleep | 75 | 150 | µA | l; VIN = 0V, CAPSEL = 1 | 3 | ||
| SCAP Quiescent Current, Backup Mode with Backup Boost in Sleep | 1 | 2 | µA | l; VIN = 0V, CAPSEL = 1 | 3 | ||
| VIN Quiescent Current, Shutdown | 5.5 | 11 | µA | CHGEN = BSTEN = CAPSEL = 1, VSYS = 0V | 3 | ||
| SCAP Quiescent Current, Shutdown | 0 | 1 | µA | l; CHGEN = BSTEN = CAPSEL = 1, VSYS = 0V | 3 | ||
| CAPFB Pin Servo Voltage | VCAPFB | 0.788 | 0.8 | 0.812 | V | l | 3 |
| CAPFB Pin Input Leakage Current | ICAPFB | -50 | 0 | 50 | nA | 3 | |
| Regulated Supercapacitor Charge Current | ICHG | 950 | 1000 | 1050 | mA | RPROG = 2k, VSCAP >1V | 3 |
| VSYS-to-VSCAP Differential Undervoltage Lockout Threshold, Falling | 30 | 50 | 70 | mV | (VSYS, VSCAP) Falling | 3 | |
| VSYS-to-VSCAP Differential Undervoltage Lockout Threshold, Rising | 100 | 150 | 200 | mV | (VSYS, VSCAP) Rising | 3 | |
| Input Current Limit Threshold Voltage (first printed row) | VIN, VCLN | 23.5 | 25 | 26.5 | mV | l | 3 |
| Input Current Limit Threshold Voltage (second printed row) | VIN, VCLN | 22 | 25 | 28 | mV | l | 3 |
| Recharge Threshold Voltage | VRECHRG | 96.2 | 97.5 | 98.8 | % | As a Percentage of the Regulated VSCAP | 3 |
| CAPGD Rising Threshold | 90 | 92.5 | 95 | % | As a Percentage of the Regulated VSCAP | 3 | |
| Step-Down Converter Switching Frequency | fOSC(BUCK) | 2 | 2.25 | 2.5 | MHz | VSCAP>1V | 3 |
| PMOS Switch Current Limit | ILIM(BUCK) | 3 | 4.3 | A | 3 | ||
| Supercapacitor Balance Point | VBAL | 49 | 50 | 51 | % | As a Percentage of VSCAP, VSCAP = 5V | 3 |
| Top/Bottom Supercapacitor Overvoltage Threshold | 2.7 | 2.8 | V | (VSCAP, VBAL) and/or VBAL Rising, CAPSEL = 1 | 3 | ||
| Top/Bottom Supercapacitor Undervoltage Threshold | -50 | -20 | mV | (VSCAP, VBAL) and/or VBAL Falling, CAPSEL = 1 | 3 | ||
| BSTFB Pin Servo Voltage | VBSTFB | 0.78 | 0.8 | 0.82 | V | l | 4 |
| BSTFB Pin Input Leakage Current | IBSTFB | -20 | 20 | nA | VBSTFB = 0.9V | 4 | |
| Programmed Boost Output Voltage Range | VSYS-BACKUP | 2.7 | 5 | V | 4 | ||
| Step-Up Converter Switching Frequency | fOSC(BST) | 1 | 1.125 | 1.25 | MHz | 4 | |
| NMOS Switch Current Limit | ILIM(BST) | 5.5 | 6.5 | 7.5 | A | 4 | |
| VSYS Overvoltage Shutdown Threshold | 5.3 | 5.5 | 5.7 | V | VSYS Rising | 4 | |
| Boost Undervoltage Lockout | 2.5 | V | Max(VSYS, VSCAP) Falling | 4 | |||
| Maximum Boost Duty Cycle | DMAX | 88 | % | 4 | |||
| NMOS Switch Leakage Current | 0 | 1 | µA | BSTEN = 1, CHGEN = 1 | 4 | ||
| PMOS Switch Leakage Current | 0 | 1 | µA | BSTEN = 1, CHGEN = 1 | 4 | ||
| RSTFB Threshold (Falling) | VRSTFB | 0.72 | 0.74 | 0.76 | V | l; VRSTFB Falling | 4 |
| RSTFB Pin Input Leakage Current | IRSTFB | -50 | 0 | 50 | nA | VRSTFB = 0.9V | 4 |
| PFI Input Threshold (first printed row) | VPFI | 1.17 | 1.19 | 1.21 | V | l; VPFI Falling | 4 |
| PFI Input Threshold (second printed row) | VPFI | 1.16 | 1.19 | 1.22 | V | l; VPFI Falling | 4 |
| PFI Pin Leakage Current | -100 | 0 | 100 | nA | VPFI = 1.3V | 4 | |
| PFO Pin Leakage Current | 0 | 1 | µA | VPFO = 5V | 4 | ||
| PFO Pin Output Low Voltage | 65 | 200 | mV | IPFO = 5mA | 4 | ||
| Logic Low Input Voltage | VIL | 0.4 | V | l; BSTEN, CHGEN, CAPSEL, CAPFLT | 4 | ||
| Logic High Input Voltage | VIH | 1.2 | V | l; BSTEN, CHGEN, CAPSEL, CAPFLT | 4 | ||
| Open-Drain Output Pin Leakage Current (SYSGD, CAPGD) | 0 | 1 | µA | 5V at Pin | 5 | ||
| Open-Drain Output Pin Output Low Voltage (SYSGD, CAPGD) | 65 | 200 | mV | 5mA Into Pin | 5 | ||
| CAPFLT Pin Leakage Current | 0 | 1 | µA | 5V at Pin | 5 | ||
| Overvoltage Protection Threshold | VOV(CUTOFF) | 6 | 6.4 | 6.8 | V | VOVSNS Rising, ROVSNS = 6.2k | 5 |
| IGATE Output Voltage Active | VOVGT | 9.4 | 12 | V | VIN = VOVSNS = 5V | 5 | |
| IGATE Voltage Under Load | VOVGT(LOAD) | 8 | 8.6 | V | 5V Through 6.2k Into OVSNS, IIGATE = 1μA | 5 | |
| Junction-to-Ambient Thermal Resistance | θJA | 43 | °C/W | 2 | |||
| Junction-to-Case Thermal Resistance | θJC | 3.4 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LTC4041EUFD#PBF - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: QFN-24-EP(4x5) (KiCad packages3D, STEP)
- 3D model files:
ltc4041eufd-pbf-etched.step/ltc4041eufd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc4041eufd-pbf.step/ltc4041eufd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
fb432e97896944d4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTC4041EUFD#PBF
**Analog Devices** · Battery Management · QFN-24-EP(4x5)
LTC4041EUFD#PBF from Analog Devices, in a QFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSYS | power_out | System voltage output that supplies the external load from the input or from the supercapacitor in backup, and must be bypassed with at least 100µF of low-ESR ceramic capacitor to GND. |
| 2 | PROG | passive | Charge-current program pin where an external resistor to GND sets full-scale charge current, with PROG servoing to 0.8V and an SCAP-to-PROG current ratio of 2500. |
| 3 | IMON | output | VSYS current monitor whose voltage is 32 times the VIN-to-CLN differential voltage, and charge current is reduced when IMON reaches 0.8V. |
| 4 | CHGEN | input | Disable input for the supercapacitor charger that enables charging when tied to GND and disables it when above 1.2V, and must not be left unconnected. |
| 5 | BSTEN | input | Disable input for the backup boost converter that enables backup when tied to GND and disables it when above 1.2V, and must not be left unconnected. |
| 6 | VIN | power_in | Input pin that can be driven directly when OVP is not used, or fed through an external N-channel FET from the input supply VPWR when OVP is required. |
| 7 | CLN | input | Negative terminal of the external input-current sense resistor between VIN and CLN, where the charger regulates to 25mV across the resistor but does not limit system current if the drop exceeds 25mV. |
| 8 | CAPFLT | output | Open-drain supercapacitor fault output that pulls low and disables charging if any single supercapacitor exceeds 2.7V or disables backup if any falls below -20mV, with a 10µA pull-down capability and tie-high to keep operation enabled. |
| 9 | BAL | passive | Supercapacitor balance point for a two-capacitor stack that the internal balancer drives to half of VSCAP, and which must be left open when only one supercapacitor is used. |
| 10 | RSTFB | input | High-impedance input to the SYSGD comparator with a 0.74V falling threshold and 20mV hysteresis, driven from an external divider between VSYS and GND. |
| 11 | SYSGD | output | Open-drain system power-good output that is pulled to GND by an internal N-channel MOSFET whenever RSTFB falls below 0.74V. |
| 12 | CAPFB | input | Supercapacitor (single or two-stack) feedback input from an external divider between SCAP and GND that nominally servos to 0.8V to program the final charge voltage. |
| 13 | CAPGD | output | Open-drain supercapacitor power-good output that stays pulled low until CAPFB rises to 92.5% of its regulation point. |
| 14 | PFO | output | Open-drain power-fail status output that is pulled to GND when PFI is below its falling threshold and becomes high impedance once PFI rises above its rising threshold. |
| 15 | IGATE | output | Gate drive for the external N-channel pass FET(s) from an internal charge pump, where the mandatory VIN-to-VSYS FET disconnects the system from the input during backup. |
| 16 | OVSNS | input | Overvoltage protection sense input that connects through a 6.2k resistor to the input supply and the pass FET drain, or is shorted to VIN if OVP is unused, and pulls IGATE to GND when it exceeds 6V (typical). |
| 17 | CPF | passive | Minimum backup time program pin where a capacitor sets tMIN-BACKUP, and which must not be tied to GND or left unconnected. |
| 18 | BSTFB | input | Feedback input for the backup boost regulator that servos to 0.8V during backup operation. |
| 19 | PFI | input | High-impedance power-fail input with a 1.19V falling threshold and 40mV hysteresis that controls PFO and sets the input voltage below which backup boost starts. |
| 20 | CAPSEL | input | Supercapacitor stack selector that must be tied above 1.2V for a two-capacitor stack or to GND for a single supercapacitor, and must not be left unconnected. |
| 21 | SW | passive | Switch pin for the buck charger and boost backup converter, connected to SCAP through a 1µH to 2.2µH inductor. |
| 22 | SW | passive | Switch pin for the buck charger and boost backup converter, connected to SCAP through a 1µH to 2.2µH inductor. |
| 23 | SCAP | bidirectional | Supercapacitor pin for a single supercapacitor or the top of a two-capacitor stack, which supplies VSYS through the boost in backup or is charged from VSYS by the buck charger. |
| 24 | VSYS | power_out | System voltage output pin that supplies the external load from the input or from the supercapacitor in backup, and must be bypassed with at least 100µF of low-ESR ceramic capacitor to GND. |
| 25 | GND | power_in | Exposed pad that must be soldered to the PCB to provide low electrical and thermal impedance ground, with a continuous ground plane on the second layer strongly recommended. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-24-EP(4x5) |
| Category | Power Management (PMIC) |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Transient Voltage | VIN | -0.3 | | 7 | V | t < 1ms, Duty Cycle < 1% | 2 |
| Steady-State Voltage (VIN, SCAP, BAL, CLN, VSYS, BSTFB, PFI, CPF, CAPFB, CAPFLT, PFO, SYSGD, OVSNS, IMON) | VIN, SCAP, BAL, CLN, VSYS, BSTFB, PFI, CPF, CAPFB, CAPFLT, PFO, SYSGD, OVSNS, IMON | -0.3 | | 6 | V | Steady state | 2 |
| Voltage (BSTEN, CHGEN, CAPGD, RSTFB, CAPSEL) | BSTEN, CHGEN, CAPGD, RSTFB, CAPSEL | -0.3 | | | V | Upper limit is [Max (VIN, VSCAP, VSYS) +0.3V]; no numeric max printed | 2 |
| IOVSNS Current | IOVSNS | -10 | | 10 | mA | | 2 |
| Current (ICAPGD, IPFO, ISYSGD) | ICAPGD, IPFO, ISYSGD | | | 10 | mA | | 2 |
| IPROG Current | IPROG | -1.1 | | | mA | | 2 |
| Operating Junction Temperature Range | TJ | -40 | | 125 | °C | Notes 2, 3 | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | Note 1 | 2 |
| Maximum Junction Temperature | TJMAX | | | 125 | °C | | 2 |
| Input Voltage Range | VIN | 2.9 | | 5.5 | V | l | 3 |
| Supercapacitor Voltage Range (Backup Boost Input) | VSCAP | | | 5.4 | V | l | 3 |
| VIN and VSYS Total Quiescent Current, Charger Mode with Charging Complete and Backup Boost Active | | | 800 | 1600 | µA | CAPSEL = 1 | 3 |
| SCAP Quiescent Current, Charger Mode with Charging Complete and Backup Boost Active | | | 13 | 26 | µA | CAPSEL = 1 | 3 |
| VIN and VSYS Total Quiescent Current, Charger Mode with Charging Complete and Backup Boost in Sleep | | | 275 | 550 | µA | CAPSEL = 1 | 3 |
| SCAP Quiescent Current, Charger Mode with Charging Complete and Backup Boost in Sleep | | | 13 | 26 | µA | CAPSEL = 1 | 3 |
| VSYS Quiescent Current, Backup Mode with Backup Boost in Sleep | | | 75 | 150 | µA | l; VIN = 0V, CAPSEL = 1 | 3 |
| SCAP Quiescent Current, Backup Mode with Backup Boost in Sleep | | | 1 | 2 | µA | l; VIN = 0V, CAPSEL = 1 | 3 |
| VIN Quiescent Current, Shutdown | | | 5.5 | 11 | µA | CHGEN = BSTEN = CAPSEL = 1, VSYS = 0V | 3 |
| SCAP Quiescent Current, Shutdown | | | 0 | 1 | µA | l; CHGEN = BSTEN = CAPSEL = 1, VSYS = 0V | 3 |
| CAPFB Pin Servo Voltage | VCAPFB | 0.788 | 0.8 | 0.812 | V | l | 3 |
| CAPFB Pin Input Leakage Current | ICAPFB | -50 | 0 | 50 | nA | | 3 |
| Regulated Supercapacitor Charge Current | ICHG | 950 | 1000 | 1050 | mA | RPROG = 2k, VSCAP >1V | 3 |
| VSYS-to-VSCAP Differential Undervoltage Lockout Threshold, Falling | | 30 | 50 | 70 | mV | (VSYS, VSCAP) Falling | 3 |
| VSYS-to-VSCAP Differential Undervoltage Lockout Threshold, Rising | | 100 | 150 | 200 | mV | (VSYS, VSCAP) Rising | 3 |
| Input Current Limit Threshold Voltage (first printed row) | VIN, VCLN | 23.5 | 25 | 26.5 | mV | l | 3 |
| Input Current Limit Threshold Voltage (second printed row) | VIN, VCLN | 22 | 25 | 28 | mV | l | 3 |
| Recharge Threshold Voltage | VRECHRG | 96.2 | 97.5 | 98.8 | % | As a Percentage of the Regulated VSCAP | 3 |
| CAPGD Rising Threshold | | 90 | 92.5 | 95 | % | As a Percentage of the Regulated VSCAP | 3 |
| Step-Down Converter Switching Frequency | fOSC(BUCK) | 2 | 2.25 | 2.5 | MHz | VSCAP>1V | 3 |
| PMOS Switch Current Limit | ILIM(BUCK) | 3 | | 4.3 | A | | 3 |
| Supercapacitor Balance Point | VBAL | 49 | 50 | 51 | % | As a Percentage of VSCAP, VSCAP = 5V | 3 |
| Top/Bottom Supercapacitor Overvoltage Threshold | | 2.7 | | 2.8 | V | (VSCAP, VBAL) and/or VBAL Rising, CAPSEL = 1 | 3 |
| Top/Bottom Supercapacitor Undervoltage Threshold | | -50 | | -20 | mV | (VSCAP, VBAL) and/or VBAL Falling, CAPSEL = 1 | 3 |
| BSTFB Pin Servo Voltage | VBSTFB | 0.78 | 0.8 | 0.82 | V | l | 4 |
| BSTFB Pin Input Leakage Current | IBSTFB | -20 | | 20 | nA | VBSTFB = 0.9V | 4 |
| Programmed Boost Output Voltage Range | VSYS-BACKUP | 2.7 | | 5 | V | | 4 |
| Step-Up Converter Switching Frequency | fOSC(BST) | 1 | 1.125 | 1.25 | MHz | | 4 |
| NMOS Switch Current Limit | ILIM(BST) | 5.5 | 6.5 | 7.5 | A | | 4 |
| VSYS Overvoltage Shutdown Threshold | | 5.3 | 5.5 | 5.7 | V | VSYS Rising | 4 |
| Boost Undervoltage Lockout | | | 2.5 | | V | Max(VSYS, VSCAP) Falling | 4 |
| Maximum Boost Duty Cycle | DMAX | | | 88 | % | | 4 |
| NMOS Switch Leakage Current | | | 0 | 1 | µA | BSTEN = 1, CHGEN = 1 | 4 |
| PMOS Switch Leakage Current | | | 0 | 1 | µA | BSTEN = 1, CHGEN = 1 | 4 |
| RSTFB Threshold (Falling) | VRSTFB | 0.72 | 0.74 | 0.76 | V | l; VRSTFB Falling | 4 |
| RSTFB Pin Input Leakage Current | IRSTFB | -50 | 0 | 50 | nA | VRSTFB = 0.9V | 4 |
| PFI Input Threshold (first printed row) | VPFI | 1.17 | 1.19 | 1.21 | V | l; VPFI Falling | 4 |
| PFI Input Threshold (second printed row) | VPFI | 1.16 | 1.19 | 1.22 | V | l; VPFI Falling | 4 |
| PFI Pin Leakage Current | | -100 | 0 | 100 | nA | VPFI = 1.3V | 4 |
| PFO Pin Leakage Current | | | 0 | 1 | µA | VPFO = 5V | 4 |
| PFO Pin Output Low Voltage | | | 65 | 200 | mV | IPFO = 5mA | 4 |
| Logic Low Input Voltage | VIL | | | 0.4 | V | l; BSTEN, CHGEN, CAPSEL, CAPFLT | 4 |
| Logic High Input Voltage | VIH | 1.2 | | | V | l; BSTEN, CHGEN, CAPSEL, CAPFLT | 4 |
| Open-Drain Output Pin Leakage Current (SYSGD, CAPGD) | | | 0 | 1 | µA | 5V at Pin | 5 |
| Open-Drain Output Pin Output Low Voltage (SYSGD, CAPGD) | | | 65 | 200 | mV | 5mA Into Pin | 5 |
| CAPFLT Pin Leakage Current | | | 0 | 1 | µA | 5V at Pin | 5 |
| Overvoltage Protection Threshold | VOV(CUTOFF) | 6 | 6.4 | 6.8 | V | VOVSNS Rising, ROVSNS = 6.2k | 5 |
| IGATE Output Voltage Active | VOVGT | 9.4 | | 12 | V | VIN = VOVSNS = 5V | 5 |
| IGATE Voltage Under Load | VOVGT(LOAD) | 8 | | 8.6 | V | 5V Through 6.2k Into OVSNS, IIGATE = 1μA | 5 |
| Junction-to-Ambient Thermal Resistance | θJA | | 43 | | °C/W | | 2 |
| Junction-to-Case Thermal Resistance | θJC | | 3.4 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `LTC4041EUFD#PBF`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm`
- 3D model: QFN-24-EP(4x5) (KiCad packages3D, STEP)
- 3D model files: `ltc4041eufd-pbf-etched.step` / `ltc4041eufd-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc4041eufd-pbf.step` / `ltc4041eufd-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589837639831887872) (26 pp, sha256 `fb432e97896944d4`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltc4041eufd-pbf-datasheet.pdf)