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LTC3625EDE#PBF

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Analog Devices Power Management - Specialized, DFN-12-EP(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LTC3625EDE#PBF

Analog Devices · Power Management - Specialized · DFN-12-EP(3x4)

LTC3625EDE#PBF from Analog Devices, in a DFN-12-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW1 output Buck regulator switch pin; the external inductor connects between SW1 and VMID, and the absolute maximum switch current (ISW1) is 3A.
2 VIN power_in Input voltage pin operating from 2.7V to 5.5V; bypass to GND with a 10µF or larger ceramic capacitor.
3 CTL input Logic input that selects single-inductor (high) or two-inductor (low) operation; it is a high-impedance input that must be tied to VIN or GND and must not be left floating.
4 VSEL input Logic input that selects the output voltage: low sets VOUT = 4.8V/4.0V and high sets VOUT = 5.3V/4.5V, with a 4.5MΩ internal pull-down when the part is enabled.
5 EN input Active-high logic enable with a 4.5MΩ internal pull-down; a low level shuts the part down and makes VOUT high impedance, and the absolute maximum rating is VIN + 0.3V.
6 PROG passive Charge current program pin; a resistor from PROG to ground sets the buck output current, the pin servos to 1.2V, and the absolute maximum PROG current is 1mA.
7 PFI input Input to the power-fail comparator with a 1.2V falling threshold, driven from an external resistor divider between VIN and GND; tie PFI to VIN if the function is not used.
8 PFO output Open-drain power-fail comparator output that is pulled low when VIN is below the divider-programmed level, with an absolute maximum current of 50mA; leave unconnected if the function is not used.
9 PGOOD output Open-drain output that goes high impedance once VOUT reaches 92.5% (typical) of its final value and is pulled low if VOUT falls to 89.5% (typical), with an absolute maximum current of 50mA.
10 VMID passive Midpoint of the two series supercapacitors that is monitored together with VOUT to enable or shut down the buck and boost converters for voltage balancing, with a 6V absolute maximum rating.
11 VOUT power_out Output voltage pin connected to the positive terminal of the top supercapacitor, with a 6V absolute maximum rating (7V transient for t < 1ms at duty cycle < 1%).
12 SW2 output Boost regulator switch pin; the external inductor connects between SW2 and VMID, SW2 must be connected to SW1 when CTL is high, and the absolute maximum switch current (ISW2) is 3A.
13 GND power_in Ground exposed pad that must be soldered to a continuous PCB ground plane directly under the part for electrical contact and rated thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package DFN-12-EP(3x4)
Category Power Management (PMIC)
Pins 13

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage Range VIN 5.5 V 2
Input Undervoltage Lockout (VIN Rising) VIN(UVLO) 2.8 2.9 3 V VSEL = VIN (LTC3625) 2
Input Undervoltage Lockout (VIN Rising) VIN(UVLO) 2.53 2.63 2.73 V VSEL = 0V (LTC3625) 2
Charger Termination Voltage VOUT(SLEEP) 5.2 5.3 5.4 V VSEL = VIN (LTC3625) 2
Charger Termination Voltage VOUT(SLEEP) 4.7 4.8 4.9 V VSEL = 0V (LTC3625) 2
Maximum Voltage Across Either Supercapacitor After Charging VTOP, VBOT 2.7 2.75 V VSEL = VIN, VOUT = 5.3V (LTC3625) 2
Maximum Voltage Across Either Supercapacitor After Charging VTOP, VBOT 2.45 2.5 V VSEL = 0V, VOUT = 4.8V (LTC3625) 2
Maximum Supercapacitor Offset After Charging 100 180 mV CTL = 0V 2
Maximum Supercapacitor Offset After Charging 50 120 mV CTL = VIN 2
Input Operating Current IVIN 135 200 µA ISW1 = ISW2 = 0µA, No Switching; CTL = VIN, VMID = 1.5V, VOUT = 2.5V (Boost Only) 3
Input Operating Current IVIN 275 400 µA ISW1 = ISW2 = 0µA, No Switching; CTL = VIN, VMID = 1.5V, VOUT = 3.5V (Buck Only) 3
Input Operating Current IVIN 365 530 µA ISW1 = ISW2 = 0µA, No Switching; CTL = 0, VMID = 1.5V, VOUT = 2.5V (Buck and Boost) 3
Input Sleep Current 23 35 µA VIN = 5.5V, VOUT = 5.4V 3
Input Sleep Current 8 15 µA VIN = 3.6V, VOUT = 5.4V 3
Input SD Current 0 1 µA VOUT = 0V 3
VOUT SD Current IVOUT 0 1 µA VOUT = 5.4V 3
VOUT Sleep Current 17 25 µA VOUT = 5.4V, VIN = 3.6V, EN = VIN 3
VOUT Sleep Current 1 2.5 µA VOUT = 5.4V, VIN = 5.5V, EN = VIN 3
PROG Servo Voltage VPROG 1.17 1.2 1.23 V VOUT = 3.5V, VMID = 1.5V 3
Programmed Buck Charge Current IBUCK 0.88 0.99 1.1 A RPROG = 143k (Note 5) 3
Programmed Buck Charge Current IBUCK 1.76 1.98 2.2 A RPROG = 71.5k (Note 5) 3
Maximum Programmed Charge Current IMAX 1.98 2.65 3.31 A RPROG = 0Ω (Fault Condition) (Note 5) 3
Boost Charge Current Peak IPEAK(BOOST) 1.59 2.12 2.65 A VOUT = 3V, VMID = 2V (Note 5) 3
Boost Charge Current Valley IVALLEY(BOOST) 1.41 1.88 2.35 A VOUT = 3V, VMID = 2V 3
PFI Falling Threshold VPFI 1.17 1.2 1.23 V 3
Input Low Logic Voltage VIL 0.4 V EN, CTL, VSEL pins 3
Input High Logic Voltage VIH 1.2 V EN, CTL, VSEL pins 3
Output Low Logic Voltage VOL 70 200 mV PGOOD, PFO pins; sinking 5mA 3
PGOOD Rising Threshold 90 92.5 95 % VOUT as a percentage of final target 3
Pin Leakage Current for PFI Pin IPFI 0 30 nA 3
VIN, VOUT transient voltage VIN, VOUT -0.3 7 V t < 1ms, Duty Cycle < 1% 2
Voltage on VIN, VOUT, VMID, PGOOD, CTL, PROG, PFI, PFO -0.3 6 V 2
Voltage on EN, VSEL -0.3 V Maximum is VIN + 0.3V 2
Current IPGOOD, IPFO IPGOOD, IPFO 50 mA 2
Current IPROG IPROG 1 mA 2
Current IVIN, ISW1, ISW2, IVOUT IVIN, ISW1, ISW2, IVOUT 3 A Note 2: internal switches survive peak current 2
Operating Junction Temperature Range -40 125 °C Notes 3, 4 2
Storage Temperature Range -65 125 °C 2
Thermal Resistance, Junction to Ambient θJA 43 °C/W 2
Boost Charge Current Peak IPEAK(BOOST) 200 mA VOUT = 1V, VMID = 2V (Note 5) 3
Boost Charge Current Valley IVALLEY(BOOST) 0 mA VOUT = 1V, VMID = 2V 3

CAD (KiCad official)

  • Symbol: LTC3625EDE#PBF
  • Footprint: Package_DFN_QFN:DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm
  • 3D model: DFN-12-EP(3x4) (KiCad packages3D, STEP)
  • 3D model files: ltc3625ede-pbf-etched.step / ltc3625ede-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc3625ede-pbf.step / ltc3625ede-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 d652144972ade687, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF