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LTC3265EFE#TRPBF

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Analog Devices Charge Pumps, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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LTC3265EFE#TRPBF

Analog Devices · Charge Pumps · TSSOP-20-EP

LTC3265EFE#TRPBF from Analog Devices, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No-connect pin, not connected to the LTC3265 die; it should be left floating or connected to ground.
2 CBST- passive Boost charge pump flying capacitor negative connection.
3 CBST+ passive Boost charge pump flying capacitor positive connection.
4 VIN_P power_in Input voltage for the boost charge pump, which should be bypassed with a low impedance ceramic capacitor.
5 EN- input Logic input where a logic high enables the inverting charge pump and the negative LDO regulator, and the pin must not be left floating.
6 BYP- passive LDO- reference bypass pin; a capacitor from BYP- to GND reduces LDO- output noise, and the pin is left floating if unused.
7 ADJ- input Feedback input for the negative LDO, which servos to a fixed voltage of -1.2V when the control loop is complete.
8 LDO- power_out Negative LDO regulator output, which requires a low ESR capacitor of at least 2µF to ground for stability.
9 VOUT- power_out Inverting charge pump output, driven to -VIN_N in constant frequency mode (MODE low) and regulated to -0.9 • VIN_N in Burst Mode operation (MODE high) per this pin description.
10 CINV- passive Inverting charge pump flying capacitor positive connection.
11 NC unconnected No-connect pin, not connected to the LTC3265 die; it should be left floating or connected to ground.
12 CINV+ passive Inverting charge pump flying capacitor negative connection.
13 VIN_N power_in Input voltage for the inverting charge pump, which must be tied to VIN_P or VOUT+ depending on the desired VOUT- and should be bypassed with a low impedance ceramic capacitor.
14 RT passive Input connection for programming the switching frequency; RT servos to a fixed 1.2V when EN+ or EN- is high, a resistor to GND sets the frequency, and tying RT to GND defaults the frequency to 500kHz.
15 EN+ input Logic input where a logic high enables the boost charge pump and the positive LDO regulator, and the pin must not be left floating.
16 MODE input Logic input selecting charge pump operation: a logic high forces Burst Mode operation, a logic low forces constant frequency open-loop operation, and the pin must not be left floating.
17 BYP+ passive LDO+ reference bypass pin; a capacitor from BYP+ to GND reduces LDO+ output noise, and the pin is left floating if unused.
18 ADJ+ input Feedback input for the positive LDO, which servos to a fixed voltage of 1.2V when the control loop is complete.
19 LDO+ power_out Positive LDO regulator output, which requires a low ESR capacitor of at least 2µF to ground for stability.
20 VOUT+ power_out Boost charge pump output, driven to 2 • VIN_P in constant frequency mode (MODE low) and regulated to 0.94 • 2 • VIN_P in Burst Mode operation (MODE high).
21 GND power_in Exposed pad ground that must be soldered to the PC board ground plane for proper functionality and rated thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20-EP
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN_P Input Voltage Range VIN_P 4.5 16 V 3
VIN_N Input Voltage Range VIN_N 4.5 32 V 3
VIN_P Quiescent Current IVIN_P 3 6 µA Shutdown, EN+ = EN- = 0V 3
VIN_P Quiescent Current IVIN_P 85 170 µA MODE = VIN_P, EN- = 0V, IVOUT+ = ILDO+ = 0mA 3
VIN_P Quiescent Current IVIN_P 110 220 µA MODE = VIN_P, IVOUT = ILDO+ = ILDO- = 0mA 3
VIN_P Quiescent Current IVIN_P 3 6 mA MODE = 0V, IVOUT+ = 0mA 3
Oscillator Frequency fOSC 450 500 550 kHz RT = GND 3
Max IVOUT+ Short-Circuit Current IVOUT+(SC) 100 220 300 mA VOUT+ = GND 3
MODE Threshold Rising VMODE(H) 1.1 2 V 3
MODE Threshold Falling VMODE(L) 0.4 1 V 3
VIN_N Quiescent Current IVIN_N 1 3 µA Shutdown, EN- = 0V 3
VIN_N Quiescent Current IVIN_N 25 50 µA MODE = VIN_P, IVOUT- = ILDO- = 0mA 3
VIN_N Quiescent Current IVIN_N 3 5 mA MODE = 0V, IVOUT- = 0mA 3
Max IVOUT- Short-Circuit Current IVOUT-(SC) 100 160 250 mA VOUT- = GND, /IVOUT-/ 3
LDO+ Output Voltage Range LDO+ 1.2 32 V 3
ADJ+ Reference Voltage VADJ+ 1.176 1.2 1.224 V ILDO+ = 1mA 3
ADJ+ Input Current IADJ+ -50 50 nA VADJ+ = 1.2V 3
LDO+ Short-Circuit Current ILDO+(SC) 50 100 mA 3
LDO+ Dropout Voltage VDROPOUT+ 400 800 mV ILDO+ = 50mA 3
EN+ Threshold Rising VEN+(H) 1.1 2 V 3
EN+ Threshold Falling VEN+(L) 0.4 1 V 3
LDO- Output Voltage Range LDO- -32 -1.2 V 3
ADJ- Reference Voltage VADJ- -1.224 -1.2 -1.176 V ILDO- = -1mA 3
ADJ- Input Current IADJ- -50 50 nA VADJ- = -1.2V 3
LDO- Short-Circuit Current ILDO-(SC) 50 100 mA /ILDO-/ 3
LDO- Dropout Voltage VDROPOUT- 200 500 mV ILDO- = -50mA 4
EN- Threshold Rising VEN-(H) 1.1 2 V 4
EN- Threshold Falling VEN-(L) 0.4 1 V 4
Absolute maximum voltage on VIN_P, EN+, EN-, MODE VIN_P, EN+, EN-, MODE -0.3 18 V 2
Absolute maximum voltage on VOUT+, VIN_N VOUT+, VIN_N -0.3 36 V 2
Absolute maximum voltage on LDO+ LDO+ -16 36 V 2
Absolute maximum voltage on VOUT-, LDO- VOUT-, LDO- -36 0.3 V 2
Absolute maximum voltage on RT, ADJ+ RT, ADJ+ -0.3 6 V 2
Absolute maximum voltage on BYP+ BYP+ -0.3 2.5 V 2
Absolute maximum voltage on ADJ- ADJ- -6 0.3 V 2
Absolute maximum voltage on BYP- BYP- -2.5 0.3 V 2
Operating Junction Temperature Range TJ -55 150 °C 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature (Soldering, 10 sec) 300 °C FE (TSSOP) only, 10 sec soldering 2
Operating temperature range (E grade, TSSOP) -40 125 °C Order information: LTC3265EFE#PBF / LTC3265EFE#TRPBF 2
Junction-to-ambient thermal resistance θJA 38 °C/W FE package (20-lead plastic TSSOP) 2
Maximum junction temperature TJMAX 150 °C FE package (20-lead plastic TSSOP) 2

CAD (KiCad official)

  • Symbol: LTC3265EFE#TRPBF
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ltc3265efe-trpbf-etched.step / ltc3265efe-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc3265efe-trpbf.step / ltc3265efe-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 0708ba47364a932e, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF