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LTC2481IDD#PBF
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Analog Devices Analog To Digital Converters (ADC), DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTC2481IDD#PBF
Analog Devices · Analog To Digital Converters (ADC) · DFN-10-EP(3x3)
LTC2481IDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF+ | input | Positive differential reference input; it may be any value between GND and VCC as long as REF+ is at least 0.1V more positive than REF-. |
| 2 | VCC | power_in | Positive supply voltage; bypass to GND (pin 8) with a 1µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible. |
| 3 | REF- | input | Negative differential reference input; it must be at least 0.1V less positive than REF+ and lie between GND and VCC. |
| 4 | IN+ | input | Positive differential analog input that may range from GND - 0.3V to VCC + 0.3V, with a bipolar differential input range of -0.5·VREF/GAIN to 0.5·VREF/GAIN; outside this range the converter produces overrange/underrange codes. |
| 5 | IN- | input | Negative differential analog input that may range from GND - 0.3V to VCC + 0.3V, forming with IN+ the bipolar input range of -0.5·VREF/GAIN to 0.5·VREF/GAIN. |
| 6 | SCL | input | I2C serial clock input; the LTC2481 acts only as a slave, shifting data into SDA on SCL rising edges and outputting data on SDA on SCL falling edges. |
| 7 | SDA | bidirectional | I2C bidirectional serial data line: high impedance in data input (write) mode, and an open-drain N-channel driver in data output (read) mode that requires an external pull-up resistor or current source to VCC. |
| 8 | GND | power_in | Ground; connect to a ground plane through a low impedance connection. |
| 9 | CA1 | input | Three-state (LOW, HIGH, or Floating) chip address control pin that sets bit CA1 of the device I2C address. |
| 10 | CA0/f0 | input | Two-state (HIGH or Floating) chip address control pin when no transition is detected; when driven by an external clock of at least 10kHz (fEOSC), it becomes the system clock with the digital filter rejection null at fEOSC/5120 and sets CA0 internally HIGH. |
| 11 | GND | power_in | Exposed pad is GND and must be soldered to the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Data Acquisition |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC) to GND | VCC | -0.3 | 6 | V | 2 | ||
| Analog Input Voltage to GND | -0.3 | V | upper limit printed as (VCC + 0.3V) | 2 | |||
| Digital Input Voltage to GND | -0.3 | V | upper limit printed as (VCC + 0.3V) | 2 | |||
| Operating Temperature Range | -40 | 85 | °C | LTC2481I | 2 | ||
| Storage Temperature Range | -65 | 125 | °C | 2 | |||
| Resolution (No Missing Codes) | 16 | Bits | 0.1 ≤ VREF ≤ VCC, -FS ≤ VIN ≤ +FS (Note 5) | 2 | |||
| Integral Nonlinearity | 2 | ppm of VREF | 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) | 2 | |||
| Integral Nonlinearity | 10 | ppm of VREF | 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) | 2 | |||
| Offset Error | 0.5 | 2.5 | µV | 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN- ≤ VCC (Note 13) | 2 | ||
| Positive Full-Scale Error | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN- = 0.25VREF | 2 | |||
| Negative Full-Scale Error | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN- = 0.75VREF, IN+ = 0.25VREF | 2 | |||
| Total Unadjusted Error | 15 | ppm of VREF | 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) | 2 | |||
| Internal PTAT Signal | 390 | 450 | mV | TA = 27°C | 2 | ||
| Programmable Gain | 1 | 256 | See Table 2a | 2 | |||
| Offset Error (2x Speed) | 0.5 | 2 | mV | 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN- ≤ VCC (Note 13) | 3 | ||
| Positive Full-Scale Error (2x Speed) | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN- = 0.25VREF | 3 | |||
| Negative Full-Scale Error (2x Speed) | 25 | ppm of VREF | 2.5V ≤ VREF ≤ VCC, IN- = 0.75VREF, IN+ = 0.25VREF | 3 | |||
| Programmable Gain (2x Speed) | 1 | 128 | See Table 2b | 3 | |||
| Reference Voltage Range (REF+, REF-) | VREF | 0.1 | V | 3 | |||
| Input Common Mode Rejection DC | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Common Mode Rejection 50Hz ±2% | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Common Mode Rejection 60Hz ±2% | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | |||
| Input Normal Mode Rejection 50Hz ±2% | 110 | 120 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 7) | 3 | ||
| Input Normal Mode Rejection 60Hz ±2% | 110 | 120 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 8) | 3 | ||
| Input Normal Mode Rejection 50Hz/60Hz ±2% | 87 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Notes 5, 9) | 3 | |||
| Reference Common Mode Rejection DC | 120 | 140 | dB | 2.5V ≤ VREF ≤ VCC, GND ≤ IN- = IN+ ≤ VCC (Note 5) | 3 | ||
| IN+ DC Leakage Current | IDC_LEAK (IN+) | -10 | 1 | 10 | nA | Sleep Mode, IN+ = GND | 4 |
| IN- DC Leakage Current | IDC_LEAK (IN-) | -10 | 1 | 10 | nA | Sleep Mode, IN- = GND | 4 |
| REF+, REF- DC Leakage Current | IDC_LEAK (VREF) | -100 | 1 | 100 | nA | Sleep Mode, VREF = VCC | 4 |
| Resistance from CA0/f0, CA1 to VCC to Set Chip Address Bit to 1 | RINH | 10 | kΩ | 4 | |||
| Resistance from CA1 to GND to Set Chip Address Bit to 0 | RINL | 10 | kΩ | 4 | |||
| Resistance from CA0/f0, CA1 to VCC or GND to Set Chip Address Bit to Float | RINF | 2 | MΩ | 4 | |||
| Low Level Output Voltage | VOL | 0.4 | V | SDA I = 3mA | 4 | ||
| Output Fall Time from VIHMIN to VILMAX | tOF | 250 | ns | Bus Load CB 10pF to 400pF (Note 14) | 4 | ||
| Low Level CA0/f0 External Oscillator | VIL(EXT,OSC) | 0.5 | V | 2.7V ≤ VCC < 5.5V | 4 | ||
| External Capacitive Load On-Chip Address Pins (CA0/f0,CA1) for Valid Float | CCAX | 10 | pF | for Valid Float | 4 | ||
| Supply Voltage | VCC | 2.7 | 5.5 | V | 4 | ||
| Supply Current | ICC | 160 | µA | Conversion Mode (Note 11) | 4 | ||
| Supply Current | ICC | 1 | 2 | µA | Sleep Mode (Note 11) | 4 | |
| External Oscillator Frequency Range | fEOSC | 10 | 1000 | kHz | 5 | ||
| External Oscillator High Period | tHEO | 0.125 | 100 | µs | 5 | ||
| External Oscillator Low Period | tLEO | 0.125 | 100 | µs | 5 | ||
| Conversion Time for 1x Speed Mode | tCONV_1 | 157.2 | 160.3 | 163.5 | ms | 50Hz Mode | 5 |
| Conversion Time for 1x Speed Mode | tCONV_1 | 131 | 133.6 | 136.3 | ms | 60Hz Mode | 5 |
| Conversion Time for 1x Speed Mode | tCONV_1 | 144.1 | 146.9 | 149.9 | ms | Simultaneous 50Hz/60Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 78.7 | 80.3 | 81.9 | ms | 50Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 65.6 | 66.9 | 68.2 | ms | 60Hz Mode | 5 |
| Conversion Time for 2x Speed Mode | tCONV_2 | 72.2 | 73.6 | 75.1 | ms | Simultaneous 50Hz/60Hz Mode | 5 |
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | 5 | ||
| Hold Time (Repeated) START Condition | tHD(SDA) | 0.6 | µs | 5 | |||
| LOW Period of the SCL Clock Pin | tLOW | 1.3 | µs | 5 | |||
| HIGH Period of the SCL Clock Pin | tHIGH | 0.6 | µs | 5 | |||
| Data Hold Time | tHD(DAT) | 0 | 0.9 | µs | 5 | ||
| Data Set-Up Time | tSU(DAT) | 100 | ns | 5 | |||
| Rise Time for Both SDA and SCL Signals | tr | 300 | ns | 5 | |||
| Fall Time for Both SDA and SCL Signals | tf | 300 | ns | 5 | |||
| Maximum Junction Temperature | TJMAX | 125 | °C | 2 | |||
| Thermal Resistance (DD package) | θJA | 43 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LTC2481IDD#PBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ltc2481idd-pbf-etched.step/ltc2481idd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc2481idd-pbf.step/ltc2481idd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (40 pp, sha256
a10a2a6a86cb7e59, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).