component
LTC2308IUF#PBF
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LTC2308IUF#PBF
Analog Devices · Analog To Digital Converters (ADCs) · QFN-24-EP(4x4)
LTC2308IUF#PBF from Analog Devices, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH3 | input | Analog input channel 3, configurable as single-ended or differential via the analog input multiplexer. |
| 2 | CH4 | input | Analog input channel 4, configurable as single-ended or differential via the analog input multiplexer. |
| 3 | CH5 | input | Analog input channel 5, configurable as single-ended or differential via the analog input multiplexer. |
| 4 | CH6 | input | Analog input channel 6, configurable as single-ended or differential via the analog input multiplexer. |
| 5 | CH7 | input | Analog input channel 7, configurable as single-ended or differential via the analog input multiplexer. |
| 6 | COM | input | Common input and reference point for all single-ended inputs; must be noise-free and tied to ground for unipolar conversions or midway between GND and REFCOMP for bipolar conversions. |
| 7 | VREF | power_in | 2.5V reference output, bypass to GND with at least 2.2µF tantalum or low-ESR ceramic capacitor; may be overdriven by an external 2.5V reference. |
| 8 | REFCOMP | bidirectional | Reference buffer output with nominal 4.096V, bypass to GND with 10µF tantalum in parallel with 0.1µF ceramic; buffer is disabled by grounding VREF so REFCOMP can be overdriven externally. |
| 9 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 10 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 11 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 12 | AVDD | power_in | 5V analog supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 13 | AVDD | power_in | 5V analog supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 14 | CONVST | input | Conversion start; a rising edge begins a conversion, and for best performance it should return low within 40ns after the conversion starts or ends. |
| 15 | SDI | input | Serial data input whose bit stream configures the ADC, latched on the rising edge of the first 6 SCK pulses. |
| 16 | SCK | input | Serial data clock that synchronizes serial transfer; SDI is latched on the rising edge and SDO transitions on the falling edge. |
| 17 | SDO | output | Serial data output of the previous conversion result, shifted out on the falling edge of each SCK pulse. |
| 18 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 19 | OVDD | power_in | Output driver supply, range 2.7V to 5.25V, bypass to GND with 0.1µF ceramic close to the pin. |
| 20 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 21 | DVDD | power_in | 5V digital supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 22 | CH0 | input | Analog input channel 0, configurable as single-ended or differential via the analog input multiplexer. |
| 23 | CH1 | input | Analog input channel 1, configurable as single-ended or differential via the analog input multiplexer. |
| 24 | CH2 | input | Analog input channel 2, configurable as single-ended or differential via the analog input multiplexer. |
| 25 | GND | power_in | Exposed pad ground, must be soldered directly to the ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-24-EP(4x4) |
| Category | ADC/DAC/Data Conversion |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resolution (No Missing Codes) | 12 | Bits | 2 | ||||
| Integral Linearity Error | INL | -1 | 0.3 | 1 | LSB | Note 6 | 2 |
| Differential Linearity Error | DNL | -1 | 0.25 | 1 | LSB | 2 | |
| Bipolar Zero Error | -6 | 1 | 6 | LSB | Note 7 | 2 | |
| Bipolar Zero Error Match | -3 | 0.3 | 3 | LSB | 2 | ||
| Unipolar Zero Error | -3 | 0.5 | 3 | LSB | Note 7 | 2 | |
| Unipolar Zero Error Match | -2 | 0.3 | 2 | LSB | 2 | ||
| Bipolar Full-Scale Error | -9 | 1 | 9 | LSB | External Reference (Note 8) | 3 | |
| Bipolar Full-Scale Error Match | -3 | 0.5 | 3 | LSB | 3 | ||
| Unipolar Full-Scale Error | -8 | 1.5 | 8 | LSB | External Reference (Note 8) | 3 | |
| Unipolar Full-Scale Error Match | -3 | 0.4 | 3 | LSB | 3 | ||
| Absolute Input Range VIN+ (CH0 to CH7) | VIN+ | -0.05 | V | Note 9; max is REFCOMP | 3 | ||
| Absolute Input Range VIN- Unipolar | VIN- | -0.05 | V | Unipolar (Note 9); max is 0.25 • REFCOMP | 3 | ||
| Absolute Input Range VIN- Bipolar | VIN- | -0.05 | V | Bipolar (Note 9); max is 0.75 • REFCOMP | 3 | ||
| Analog Input Leakage Current | IIN | -1 | 1 | µA | 3 | ||
| Signal-to-(Noise + Distortion) Ratio | SINAD | 71 | 73.3 | dB | fIN = 1kHz | 3 | |
| Signal-to-Noise Ratio | SNR | 71 | 73.4 | dB | fIN = 1kHz | 3 | |
| Total Harmonic Distortion | THD | -90 | -78 | dB | fIN = 1kHz, First 5 Harmonics | 3 | |
| Spurious Free Dynamic Range | SFDR | 80 | 90 | dB | fIN = 1kHz | 3 | |
| VREF Output Voltage | VREF | 2.47 | 2.5 | 2.53 | V | IOUT = 0 | 4 |
| VREF Output Tempco | 25 | ppm/°C | IOUT = 0 | 4 | |||
| VREF Output Impedance | 8 | kW | -0.1mA ≤ IOUT ≤ 0.1mA | 4 | |||
| VREFCOMP Output Voltage | VREFCOMP | 4.096 | V | IOUT = 0 | 4 | ||
| VREF Line Regulation | 0.8 | mV/V | AVDD = 4.75V to 5.25V | 4 | |||
| High Level Input Voltage | VIH | 2.4 | V | DVDD = 5.25V | 4 | ||
| Low Level Input Voltage | VIL | 0.8 | V | DVDD = 4.75V | 4 | ||
| High Level Input Current | IIN | -10 | 10 | µA | VIN = VDD | 4 | |
| High Level Output Voltage | VOH | 4 | 4.74 | V | OVDD = 4.75V, IOUT = -200µA (min); IOUT = -10µA (typ) | 4 | |
| Low Level Output Voltage | VOL | 0.05 | 0.4 | V | OVDD = 4.75V, IOUT = 1.6mA (max); IOUT = 160µA (typ) | 4 | |
| Hi-Z Output Leakage | IOZ | -10 | 10 | µA | VOUT = 0V to OVDD, CONVST High | 4 | |
| Analog Supply Voltage | AVDD | 4.75 | 5 | 5.25 | V | 4 | |
| Digital Supply Voltage | DVDD | 4.75 | 5 | 5.25 | V | 4 | |
| Output Driver Supply Voltage | OVDD | 2.7 | 5.25 | V | 4 | ||
| Supply Current | IDD | 3.5 | 4.2 | mA | CL = 25pF | 4 | |
| Supply Current Nap Mode | IDD | 180 | 400 | µA | CONVST = 5V, Conversion Done | 4 | |
| Supply Current Sleep Mode | IDD | 7 | 20 | µA | CONVST = 5V, Conversion Done | 4 | |
| Maximum Sampling Frequency | fSMPL(MAX) | 500 | kHz | 5 | |||
| Shift Clock Frequency | fSCK | 40 | MHz | 5 | |||
| CONVST High Time | tWHCONV | 20 | ns | Note 9 | 5 | ||
| Hold Time SDI After SCK↑ | tHD | 2.5 | ns | 5 | |||
| Setup Time SDI Valid Before SCK↑ | tSUDI | 0 | ns | 5 | |||
| SCK High Time | tWHCLK | 10 | ns | fSCK = fSCK(MAX) | 5 | ||
| SCK Low Time | tWLCLK | 10 | ns | fSCK = fSCK(MAX) | 5 | ||
| CONVST Low Time During Data Transfer | tWLCONVST | 410 | ns | Note 9 | 5 | ||
| Hold Time CONVST Low After Last SCK↓ | tHCONVST | 20 | ns | Note 9 | 5 | ||
| Conversion Time | tCONV | 1.3 | 1.6 | µs | 5 | ||
| Acquisition Time | tACQ | 240 | ns | 7th SCK↑ to CONVST↑ (Note 9) | 5 | ||
| SDO Data Valid After SCK↓ | tdDO | 10.8 | 12.5 | ns | CL = 25pF (Note 9) | 5 | |
| SDO Hold Time After SCK↓ | thDO | 4 | ns | CL = 25pF | 5 | ||
| SDO Valid After CONVST↓ | ten | 11 | 15 | ns | CL = 25pF | 5 | |
| Bus Relinquish Time | tdis | 11 | 15 | ns | CL = 25pF | 5 | |
| Supply Voltage (AVDD, DVDD, OVDD) | 6 | V | 2 | ||||
| Power Dissipation | 500 | mW | 2 | ||||
| Operating Temperature Range LTC2308I | -40 | 85 | °C | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Thermal Resistance Junction to Ambient | θJA | 37 | °C/W | UF package | 2 |
CAD (KiCad official)
- Symbol:
LTC2308IUF#PBF - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
ltc2308iuf-pbf-etched.step/ltc2308iuf-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc2308iuf-pbf.step/ltc2308iuf-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (22 pp, sha256
743f34ca5cdeb0f6, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTC2308IUF#PBF
**Analog Devices** · Analog To Digital Converters (ADCs) · QFN-24-EP(4x4)
LTC2308IUF#PBF from Analog Devices, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH3 | input | Analog input channel 3, configurable as single-ended or differential via the analog input multiplexer. |
| 2 | CH4 | input | Analog input channel 4, configurable as single-ended or differential via the analog input multiplexer. |
| 3 | CH5 | input | Analog input channel 5, configurable as single-ended or differential via the analog input multiplexer. |
| 4 | CH6 | input | Analog input channel 6, configurable as single-ended or differential via the analog input multiplexer. |
| 5 | CH7 | input | Analog input channel 7, configurable as single-ended or differential via the analog input multiplexer. |
| 6 | COM | input | Common input and reference point for all single-ended inputs; must be noise-free and tied to ground for unipolar conversions or midway between GND and REFCOMP for bipolar conversions. |
| 7 | VREF | power_in | 2.5V reference output, bypass to GND with at least 2.2µF tantalum or low-ESR ceramic capacitor; may be overdriven by an external 2.5V reference. |
| 8 | REFCOMP | bidirectional | Reference buffer output with nominal 4.096V, bypass to GND with 10µF tantalum in parallel with 0.1µF ceramic; buffer is disabled by grounding VREF so REFCOMP can be overdriven externally. |
| 9 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 10 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 11 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 12 | AVDD | power_in | 5V analog supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 13 | AVDD | power_in | 5V analog supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 14 | CONVST | input | Conversion start; a rising edge begins a conversion, and for best performance it should return low within 40ns after the conversion starts or ends. |
| 15 | SDI | input | Serial data input whose bit stream configures the ADC, latched on the rising edge of the first 6 SCK pulses. |
| 16 | SCK | input | Serial data clock that synchronizes serial transfer; SDI is latched on the rising edge and SDO transitions on the falling edge. |
| 17 | SDO | output | Serial data output of the previous conversion result, shifted out on the falling edge of each SCK pulse. |
| 18 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 19 | OVDD | power_in | Output driver supply, range 2.7V to 5.25V, bypass to GND with 0.1µF ceramic close to the pin. |
| 20 | GND | power_in | Ground, must be connected to a solid ground plane. |
| 21 | DVDD | power_in | 5V digital supply, range 4.75V to 5.25V, bypass to GND with 0.1µF ceramic and 10µF tantalum in parallel. |
| 22 | CH0 | input | Analog input channel 0, configurable as single-ended or differential via the analog input multiplexer. |
| 23 | CH1 | input | Analog input channel 1, configurable as single-ended or differential via the analog input multiplexer. |
| 24 | CH2 | input | Analog input channel 2, configurable as single-ended or differential via the analog input multiplexer. |
| 25 | GND | power_in | Exposed pad ground, must be soldered directly to the ground plane. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-24-EP(4x4) |
| Category | ADC/DAC/Data Conversion |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resolution (No Missing Codes) | | 12 | | | Bits | | 2 |
| Integral Linearity Error | INL | -1 | 0.3 | 1 | LSB | Note 6 | 2 |
| Differential Linearity Error | DNL | -1 | 0.25 | 1 | LSB | | 2 |
| Bipolar Zero Error | | -6 | 1 | 6 | LSB | Note 7 | 2 |
| Bipolar Zero Error Match | | -3 | 0.3 | 3 | LSB | | 2 |
| Unipolar Zero Error | | -3 | 0.5 | 3 | LSB | Note 7 | 2 |
| Unipolar Zero Error Match | | -2 | 0.3 | 2 | LSB | | 2 |
| Bipolar Full-Scale Error | | -9 | 1 | 9 | LSB | External Reference (Note 8) | 3 |
| Bipolar Full-Scale Error Match | | -3 | 0.5 | 3 | LSB | | 3 |
| Unipolar Full-Scale Error | | -8 | 1.5 | 8 | LSB | External Reference (Note 8) | 3 |
| Unipolar Full-Scale Error Match | | -3 | 0.4 | 3 | LSB | | 3 |
| Absolute Input Range VIN+ (CH0 to CH7) | VIN+ | -0.05 | | | V | Note 9; max is REFCOMP | 3 |
| Absolute Input Range VIN- Unipolar | VIN- | -0.05 | | | V | Unipolar (Note 9); max is 0.25 • REFCOMP | 3 |
| Absolute Input Range VIN- Bipolar | VIN- | -0.05 | | | V | Bipolar (Note 9); max is 0.75 • REFCOMP | 3 |
| Analog Input Leakage Current | IIN | -1 | | 1 | µA | | 3 |
| Signal-to-(Noise + Distortion) Ratio | SINAD | 71 | 73.3 | | dB | fIN = 1kHz | 3 |
| Signal-to-Noise Ratio | SNR | 71 | 73.4 | | dB | fIN = 1kHz | 3 |
| Total Harmonic Distortion | THD | | -90 | -78 | dB | fIN = 1kHz, First 5 Harmonics | 3 |
| Spurious Free Dynamic Range | SFDR | 80 | 90 | | dB | fIN = 1kHz | 3 |
| VREF Output Voltage | VREF | 2.47 | 2.5 | 2.53 | V | IOUT = 0 | 4 |
| VREF Output Tempco | | | 25 | | ppm/°C | IOUT = 0 | 4 |
| VREF Output Impedance | | | 8 | | kW | -0.1mA ≤ IOUT ≤ 0.1mA | 4 |
| VREFCOMP Output Voltage | VREFCOMP | | 4.096 | | V | IOUT = 0 | 4 |
| VREF Line Regulation | | | 0.8 | | mV/V | AVDD = 4.75V to 5.25V | 4 |
| High Level Input Voltage | VIH | 2.4 | | | V | DVDD = 5.25V | 4 |
| Low Level Input Voltage | VIL | | | 0.8 | V | DVDD = 4.75V | 4 |
| High Level Input Current | IIN | -10 | | 10 | µA | VIN = VDD | 4 |
| High Level Output Voltage | VOH | 4 | 4.74 | | V | OVDD = 4.75V, IOUT = -200µA (min); IOUT = -10µA (typ) | 4 |
| Low Level Output Voltage | VOL | | 0.05 | 0.4 | V | OVDD = 4.75V, IOUT = 1.6mA (max); IOUT = 160µA (typ) | 4 |
| Hi-Z Output Leakage | IOZ | -10 | | 10 | µA | VOUT = 0V to OVDD, CONVST High | 4 |
| Analog Supply Voltage | AVDD | 4.75 | 5 | 5.25 | V | | 4 |
| Digital Supply Voltage | DVDD | 4.75 | 5 | 5.25 | V | | 4 |
| Output Driver Supply Voltage | OVDD | 2.7 | | 5.25 | V | | 4 |
| Supply Current | IDD | | 3.5 | 4.2 | mA | CL = 25pF | 4 |
| Supply Current Nap Mode | IDD | | 180 | 400 | µA | CONVST = 5V, Conversion Done | 4 |
| Supply Current Sleep Mode | IDD | | 7 | 20 | µA | CONVST = 5V, Conversion Done | 4 |
| Maximum Sampling Frequency | fSMPL(MAX) | 500 | | | kHz | | 5 |
| Shift Clock Frequency | fSCK | 40 | | | MHz | | 5 |
| CONVST High Time | tWHCONV | 20 | | | ns | Note 9 | 5 |
| Hold Time SDI After SCK↑ | tHD | 2.5 | | | ns | | 5 |
| Setup Time SDI Valid Before SCK↑ | tSUDI | 0 | | | ns | | 5 |
| SCK High Time | tWHCLK | 10 | | | ns | fSCK = fSCK(MAX) | 5 |
| SCK Low Time | tWLCLK | 10 | | | ns | fSCK = fSCK(MAX) | 5 |
| CONVST Low Time During Data Transfer | tWLCONVST | 410 | | | ns | Note 9 | 5 |
| Hold Time CONVST Low After Last SCK↓ | tHCONVST | 20 | | | ns | Note 9 | 5 |
| Conversion Time | tCONV | | 1.3 | 1.6 | µs | | 5 |
| Acquisition Time | tACQ | 240 | | | ns | 7th SCK↑ to CONVST↑ (Note 9) | 5 |
| SDO Data Valid After SCK↓ | tdDO | | 10.8 | 12.5 | ns | CL = 25pF (Note 9) | 5 |
| SDO Hold Time After SCK↓ | thDO | 4 | | | ns | CL = 25pF | 5 |
| SDO Valid After CONVST↓ | ten | | 11 | 15 | ns | CL = 25pF | 5 |
| Bus Relinquish Time | tdis | | 11 | 15 | ns | CL = 25pF | 5 |
| Supply Voltage (AVDD, DVDD, OVDD) | | | | 6 | V | | 2 |
| Power Dissipation | | | | 500 | mW | | 2 |
| Operating Temperature Range LTC2308I | | -40 | | 85 | °C | | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Junction Temperature | TJMAX | | | 150 | °C | | 2 |
| Thermal Resistance Junction to Ambient | θJA | | 37 | | °C/W | UF package | 2 |
## CAD (KiCad official)
- Symbol: `LTC2308IUF#PBF`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `ltc2308iuf-pbf-etched.step` / `ltc2308iuf-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ltc2308iuf-pbf.step` / `ltc2308iuf-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/2308fc.pdf) (22 pp, sha256 `743f34ca5cdeb0f6`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ltc2308iuf-pbf-datasheet.pdf)