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LTC1854CG#TRPBF

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Analog Devices Analog To Digital Converters (ADC), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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LTC1854CG#TRPBF

Analog Devices · Analog To Digital Converters (ADC) · SSOP-28-208mil

LTC1854CG#TRPBF from Analog Devices, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COM passive Common input is the negative reference point for all single-ended inputs and must be free of noise, typically tied to the analog ground plane; analog input range is ±10V with ±30V fault protection.
2 CH0 passive Analog MUX input CH0 accepts a ±10V input range and is fault protected to ±30V.
3 CH1 passive Analog MUX input CH1 accepts a ±10V input range and is fault protected to ±30V.
4 CH2 passive Analog MUX input CH2 accepts a ±10V input range and is fault protected to ±30V.
5 CH3 passive Analog MUX input CH3 accepts a ±10V input range and is fault protected to ±30V.
6 CH4 passive Analog MUX input CH4 accepts a ±10V input range and is fault protected to ±30V.
7 CH5 passive Analog MUX input CH5 accepts a ±10V input range and is fault protected to ±30V.
8 CH6 passive Analog MUX input CH6 accepts a ±10V input range and is fault protected to ±30V.
9 CH7 passive Analog MUX input CH7 accepts a ±10V input range and is fault protected to ±30V.
10 MUXOUT+ passive Positive MUX output must be connected to ADC+ for normal operation.
11 MUXOUT- passive Negative MUX output must be connected to ADC- for normal operation.
12 ADC+ passive Positive analog input to the analog-to-digital converter, connected to MUXOUT+ for normal operation.
13 ADC- passive Negative analog input to the analog-to-digital converter, connected to MUXOUT- for normal operation.
14 AGND1 power_in Analog ground.
15 VREF power_out 2.5V reference output that must be bypassed to analog ground with a 1µF tantalum capacitor.
16 REFCOMP power_out Reference buffer output with nominal output voltage of 4.096V, bypassed to analog ground with a 10µF tantalum and a 0.1µF ceramic capacitor.
17 AGND2 power_in Analog ground.
18 AGND3 power_in Analog ground; this pin is the substrate connection.
19 AVDD power_in 5V analog supply, bypassed to analog ground with a 0.1µF ceramic and a 10µF tantalum capacitor.
20 DVDD power_in 5V digital supply, bypassed to digital ground with a 0.1µF ceramic and a 10µF tantalum capacitor.
21 OVDD power_in Positive supply for the digital output buffers, specified from 3V to 5V and bypassed to digital ground with a 0.1µF ceramic and a 10µF tantalum capacitor.
22 BUSY output Converter status output that is low while a conversion is in progress.
23 SDO output Serial data output, enabled by RD low.
24 DGND power_in Digital ground.
25 SDI input Serial data input, ignored when RD is high.
26 SCK input Serial data clock, ignored when RD is high.
27 RD input Active-low read input that enables the SDO output and the serial interface.
28 CONVST input Conversion start input; the ADC starts a conversion on the rising edge of CONVST.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-28-208mil
Category Data Acquisition
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive Supply Voltage 4.75 5 5.25 V Notes 9 and 10 4
Integral Linearity Error -1 1 LSB 2
Differential Linearity Error -1 1 LSB 2
Bipolar Zero Error -5 5 LSB 2
Bipolar Zero Error Drift -0.1 0.1 ppm/°C 2
Bipolar Full-Scale Error, External Reference -0.34 0.34 % External reference (Note 11) 2
Bipolar Full-Scale Error, Internal Reference -0.45 0.45 % Internal reference (Note 11) 2
Bipolar Full-Scale Error Drift, External Reference -2.5 2.5 ppm/°C External reference 2
Bipolar Full-Scale Error Drift, Internal Reference -7 7 ppm/°C Internal reference 2
Input Common Mode Range -10 10 V 2
Analog Input Range -10 10 V CH0 to CH7, COM 3
Analog Input Range, ADC+ and ADC- -2.048 2.048 V ADC- (Note 3) 3
Input Leakage Current -1 1 µA ADC+, ADC-, CONVST = Low 3
VREF Output Voltage VREF 2.475 2.5 2.525 V IOUT = 0 4
VREF Output Temperature Coefficient -10 10 ppm/°C IOUT = 0 4
High Level Input Voltage VIH 2.4 V VDD = 5.25V 4
Low Level Input Voltage VIL 0.8 V VDD = 4.75V 4
Digital Input Current IIN -10 10 µA VIN = 0V to VDD 4
High Level Output Voltage VOH 4.74 V VDD = 4.75V, IO = -10µA, OVDD = VDD 4
High Level Output Voltage VOH 4 V VDD = 4.75V, IO = -200µA, OVDD = VDD 4
Low Level Output Voltage VOL 0.4 V VDD = 4.75V, IO = 1.6mA, OVDD = VDD 4
Hi-Z Output Leakage IOZ -10 10 µA VOUT = 0V to VDD, RD = High 4
Output Source Current ISOURCE -10 mA VOUT = 0V 4
Output Sink Current ISINK 10 mA VOUT = VDD 4
Positive Supply Current, Nap Mode 8 mA 4
Resolution 12 Bits 2
Maximum Sampling Frequency Through CH0 to CH7 Inputs fSAMPLE(MAX) 100 kHz Through CH0 to CH7 Inputs 5
Maximum Sampling Frequency Through ADC+, ADC- Only fSAMPLE(MAX) 166 kHz Through ADC+, ADC- Only 5
Acquisition Time Through CH0 to CH7 Inputs tACQ 1 µs Through CH0 to CH7 Inputs 5
Acquisition Time Through ADC+, ADC- Only tACQ 4 µs Through ADC+, ADC- Only 5
Conversion Time tCONV 4 5 µs 5
SCK Frequency fSCK 0 20 MHz Note 13 5
CONVST High Time t1 40 ns 5
SCK Period t3 50 ns 5
SCK High t4 10 ns 5
SCK Low t5 10 ns 5
Delay Time, SCK↓ to SDO Valid t6 25 45 ns CL = 25pF, See Test Circuits 5
RD↓ to SCK Setup Time t9 20 ns 5
SDI Hold Time After SCK↑ t11 7 ns 5
Supply Voltage (OVDD = DVDD = AVDD = VDD) VDD 6 V 2
Ground Voltage Difference, DGND, AGND1, AGND2, AGND3 -0.3 0.3 V 2
Analog Input Voltage, CH0 to CH7, COM -30 30 V 2
Digital Input Voltage 10 V Note 4 2
Power Dissipation 500 mW 2
Operating Temperature Range 0 70 °C LTC1854C (C grade) 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (Soldering, 10 sec) 300 °C 10 sec 2
Maximum Junction Temperature TJMAX 125 °C 2
Thermal Resistance, Junction to Ambient θJA 160 °C/W 2
Transition Noise 0.06 LSBRMS 2
Signal-to-(Noise + Distortion) Ratio S/(N + D) 74 dB 1kHz Input Signal 3
Total Harmonic Distortion, First Five Harmonics THD -102 dB 1kHz Input Signal 3
Channel-to-Channel Isolation -120 dB 1kHz Input Signal 3
-3dB Input Bandwidth 1 MHz 3
Aperture Delay -70 ns 3
Aperture Jitter 60 ps 3
VREF Output Impedance 8 kΩ -0.1mA ≤ IOUT ≤ 0.1mA 4
VREFCOMP Output Voltage 4.096 V IOUT = 0 4
Impedance, CH0 to CH7, COM 31 kΩ 3
Capacitance, CH0 to CH7, COM 5 pF 3

CAD (KiCad official)

  • Symbol: LTC1854CG#TRPBF
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: ltc1854cg-trpbf-etched.step / ltc1854cg-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc1854cg-trpbf.step / ltc1854cg-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 b4b0460cd0e4ba75, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF