component
LTA8062XS8
Public Made by Adomby adom
Linearin(先积集成) , SOIC-8L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LTA8062XS8
Linearin(先积集成) · IC · SOIC-8L
LTA8062XS8 from Linearin(先积集成), in a SOIC-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail with short-circuit current of ±45 mA. |
| 2 | -INA | input | Amplifier A inverting input, voltage range from VS- to VS+ - 1.5 V. |
| 3 | +INA | input | Amplifier A non-inverting input, same voltage range as -IN (VS- to VS+ - 1.5 V). |
| 4 | -VS | power_in | Negative power supply, normally tied to ground; VS+ to VS- must be 4.5 V to 48 V. |
| 5 | +INB | input | Amplifier B non-inverting input, same voltage range as -IN (VS- to VS+ - 1.5 V). |
| 6 | -INB | input | Amplifier B inverting input, voltage range from VS- to VS+ - 1.5 V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail with short-circuit current of ±45 mA. |
| 8 | +VS | power_in | Positive power supply, 4.5 V to 48 V (split supplies allowed if VS+ to VS- is 4.5 V to 48 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin(先积集成) |
| Package | SOIC-8L |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VS | 4.5 | 48 | V | TA = −40 to +125 ℃ | 4 | |
| Operating temperature range | TA | -40 | 125 | ºC | 4 | ||
| Input offset voltage | VOS | -350 | 75 | 350 | μV | VS = 4.5 to 48 V, TA = +25 °C | 3 |
| Offset voltage drift | VOS TC | -1.5 | 1.5 | μV/ºC | TA = −40 to +125 °C | 3 | |
| Power supply rejection ratio | PSRR | 10 | μV/V | VS = 4.5 to 48 V, VCM = 0.1 V, TA = −40 to +125 °C | 3 | ||
| Input bias current | IB | 150 | pA | TA = −40 to +85 ℃ | 3 | ||
| Input bias current | IB | 600 | pA | TA = −40 to +125 ℃ | 3 | ||
| Common-mode rejection ratio | CMRR | 102 | dB | VCM = 0.1 to 38 V, TA = −40 to +125 °C | 3 | ||
| Common-mode rejection ratio | CMRR | 83 | dB | VCM = 0.1 to 3 V, TA = −40 to +125 °C | 3 | ||
| Open-loop voltage gain | AVOL | 120 | dB | TA = −40 to +125 °C | 3 | ||
| Open-loop voltage gain | AVOL | 112 | dB | VS = 5 V, VO = 0.1 to 4.9 V, TA = −40 to +125 °C | 4 | ||
| Short-circuit current | ISC | -45 | 45 | mA | 4 | ||
| Supply voltage, VS+ to VS- | 60 | V | VS+ to VS- | 2 | |||
| Signal input terminals: current | -10 | 10 | mA | 2 | |||
| Electrostatic discharge voltage, human body model | 2000 | V | HBM, per MIL-STD-883J / Method 3015.9 | 2 | |||
| Electrostatic discharge voltage, charged device model | 2000 | V | CDM, per ESDA/JEDEC JS-002-2014 | 2 | |||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 2 | ||
| Junction temperature | TJ | 150 | ℃ | 2 | |||
| Lead temperature range | 260 | ℃ | Soldering 10 sec | 2 | |||
| Package thermal resistance, junction to ambient | θJA | 125 | ºC/W | SOIC-8L | 4 |
CAD (KiCad official)
- Symbol:
LTA8062XS8 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8L (KiCad packages3D, STEP)
- 3D model files:
lta8062xs8-etched.step/lta8062xs8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lta8062xs8.step/lta8062xs8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Linearin(先积集成) datasheet (13 pp, sha256
4b2ab2f5c5c93a5e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LTA8062XS8
**Linearin(先积集成)** · IC · SOIC-8L
LTA8062XS8 from Linearin(先积集成), in a SOIC-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTA | output | Amplifier A output, rail-to-rail with short-circuit current of ±45 mA. |
| 2 | -INA | input | Amplifier A inverting input, voltage range from VS- to VS+ - 1.5 V. |
| 3 | +INA | input | Amplifier A non-inverting input, same voltage range as -IN (VS- to VS+ - 1.5 V). |
| 4 | -VS | power_in | Negative power supply, normally tied to ground; VS+ to VS- must be 4.5 V to 48 V. |
| 5 | +INB | input | Amplifier B non-inverting input, same voltage range as -IN (VS- to VS+ - 1.5 V). |
| 6 | -INB | input | Amplifier B inverting input, voltage range from VS- to VS+ - 1.5 V. |
| 7 | OUTB | output | Amplifier B output, rail-to-rail with short-circuit current of ±45 mA. |
| 8 | +VS | power_in | Positive power supply, 4.5 V to 48 V (split supplies allowed if VS+ to VS- is 4.5 V to 48 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Linearin(先积集成) |
| Package | SOIC-8L |
| Category | |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VS | 4.5 | | 48 | V | TA = −40 to +125 ℃ | 4 |
| Operating temperature range | TA | -40 | | 125 | ºC | | 4 |
| Input offset voltage | VOS | -350 | 75 | 350 | μV | VS = 4.5 to 48 V, TA = +25 °C | 3 |
| Offset voltage drift | VOS TC | -1.5 | | 1.5 | μV/ºC | TA = −40 to +125 °C | 3 |
| Power supply rejection ratio | PSRR | | | 10 | μV/V | VS = 4.5 to 48 V, VCM = 0.1 V, TA = −40 to +125 °C | 3 |
| Input bias current | IB | | | 150 | pA | TA = −40 to +85 ℃ | 3 |
| Input bias current | IB | | | 600 | pA | TA = −40 to +125 ℃ | 3 |
| Common-mode rejection ratio | CMRR | 102 | | | dB | VCM = 0.1 to 38 V, TA = −40 to +125 °C | 3 |
| Common-mode rejection ratio | CMRR | 83 | | | dB | VCM = 0.1 to 3 V, TA = −40 to +125 °C | 3 |
| Open-loop voltage gain | AVOL | 120 | | | dB | TA = −40 to +125 °C | 3 |
| Open-loop voltage gain | AVOL | 112 | | | dB | VS = 5 V, VO = 0.1 to 4.9 V, TA = −40 to +125 °C | 4 |
| Short-circuit current | ISC | -45 | | 45 | mA | | 4 |
| Supply voltage, VS+ to VS- | | | | 60 | V | VS+ to VS- | 2 |
| Signal input terminals: current | | -10 | | 10 | mA | | 2 |
| Electrostatic discharge voltage, human body model | | | | 2000 | V | HBM, per MIL-STD-883J / Method 3015.9 | 2 |
| Electrostatic discharge voltage, charged device model | | | | 2000 | V | CDM, per ESDA/JEDEC JS-002-2014 | 2 |
| Storage temperature range | Tstg | -65 | | 150 | ℃ | | 2 |
| Junction temperature | TJ | | | 150 | ℃ | | 2 |
| Lead temperature range | | | | 260 | ℃ | Soldering 10 sec | 2 |
| Package thermal resistance, junction to ambient | θJA | | 125 | | ºC/W | SOIC-8L | 4 |
## CAD (KiCad official)
- Symbol: `LTA8062XS8`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8L (KiCad packages3D, STEP)
- 3D model files: `lta8062xs8-etched.step` / `lta8062xs8-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lta8062xs8.step` / `lta8062xs8.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Linearin(先积集成) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603166597452750848) (13 pp, sha256 `4b2ab2f5c5c93a5e`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lta8062xs8-datasheet.pdf)