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LT8610IMSE#PBF

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Analog Devices DC-DC Converters, MSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT8610IMSE#PBF

Analog Devices · DC-DC Converters · MSOP-16-EP

LT8610IMSE#PBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input External clock synchronization input that must be grounded for Burst Mode operation at low loads, tied to a clock or to INTVCC for pulse-skipping mode, and never left floating; a DC voltage of 3V or higher is needed for pulse-skipping.
2 TR/SS passive Output tracking and soft-start pin where a voltage below 0.97V forces FB to follow it, an internal 2.2µA pull-up sets the output ramp rate, and it is pulled to ground through 230Ω during shutdown and fault conditions.
3 RT passive A resistor connected between RT and ground sets the switching frequency.
4 EN/UV input Shuts the LT8610 down when low and enables it when high, with a hysteretic threshold of 1.00V rising and 0.96V falling, and it is tied to VIN if shutdown is not used.
5 VIN power_in Supply pin for internal circuitry and the internal top power switch that must be tied together with pin 6 and locally bypassed.
6 VIN power_in Supply pin for internal circuitry and the internal top power switch that must be tied together with pin 5 and locally bypassed.
7 PGND power_in Power switch ground that is the return path of the internal bottom-side power switch and must be tied together with pin 8.
8 PGND power_in Power switch ground that is the return path of the internal bottom-side power switch and must be tied together with pin 7.
9 SW output Output of the internal power switches that must be tied together with pins 10 and 11 and connected to the inductor and boost capacitor, with a small PCB node.
10 SW output Output of the internal power switches that must be tied together with pins 9 and 11 and connected to the inductor and boost capacitor, with a small PCB node.
11 SW output Output of the internal power switches that must be tied together with pins 9 and 10 and connected to the inductor and boost capacitor, with a small PCB node.
12 BST power_out Provides a drive voltage higher than the input voltage to the top power switch and requires a 0.1µF boost capacitor placed as close to the IC as possible.
13 INTVCC power_out Internal 3.4V regulator bypass pin with maximum output current of 20mA that must not be loaded externally and needs at least a 1µF low ESR ceramic capacitor to power ground.
14 BIAS power_in Supplies the internal regulator instead of VIN when tied above 3.1V, and it should be tied to VOUT for output voltages of 3.3V and above.
15 PG output Open-drain power-good output that remains low until FB is within ±9% of the regulation voltage with no fault condition, and is valid when VIN is above 3.4V.
16 FB input Feedback pin regulated to 0.970V that receives the feedback divider tap and a phase lead capacitor (typically 4.7pF to 10pF) connected to VOUT.
17 GND power_in Exposed pad ground that must be connected to the negative terminal of the input capacitor and soldered to the PCB to lower thermal resistance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-16-EP
Category Power Management ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Minimum Input Voltage 2.9 3.4 V 2
VIN Quiescent Current 1 3 µA VEN/UV = 0V, VSYNC = 0V 2
VIN Quiescent Current (full operating temperature range) 1 8 µA VEN/UV = 0V, VSYNC = 0V, l (full temp range) 2
VIN Quiescent Current, not switching 1.7 4 µA VEN/UV = 2V, Not Switching, VSYNC = 0V 2
VIN Quiescent Current, not switching (full operating temperature range) 1.7 10 µA VEN/UV = 2V, Not Switching, VSYNC = 0V, l (full temp range) 2
VIN Quiescent Current, pulse-skipping 0.24 0.5 mA VEN/UV = 2V, Not Switching, VSYNC = 2V 2
VIN Current in Regulation 24 50 µA VOUT = 0.97V, VIN = 6V, Output Load = 100µA 2
VIN Current in Regulation 210 350 µA VOUT = 0.97V, VIN = 6V, Output Load = 1mA 2
Feedback Reference Voltage 0.964 0.97 0.976 V VIN = 6V, ILOAD = 0.5A 2
Feedback Reference Voltage (full operating temperature range) 0.958 0.97 0.982 V VIN = 6V, ILOAD = 0.5A, l (full temp range) 2
Feedback Voltage Line Regulation 0.004 0.02 %/V VIN = 4.0V to 42V, ILOAD = 0.5A, l 2
Feedback Pin Input Current -20 20 nA VFB = 1V 2
INTVCC Voltage 3.23 3.4 3.57 V ILOAD = 0mA, VBIAS = 0V 2
INTVCC Voltage 3.25 3.29 3.35 V ILOAD = 0mA, VBIAS = 3.3V 2
INTVCC Undervoltage Lockout 2.5 2.6 2.7 V 2
Minimum On-Time 30 50 70 ns ILOAD = 1A, SYNC = 0V, l 2
Minimum On-Time 30 45 65 ns ILOAD = 1A, SYNC = 3.3V, l 2
Minimum Off-Time 50 80 110 ns 2
Oscillator Frequency 180 210 240 kHz RT = 221k, ILOAD = 1A, l 3
Oscillator Frequency 665 700 735 kHz RT = 60.4k, ILOAD = 1A, l 3
Oscillator Frequency 1.85 2 2.15 MHz RT = 18.2k, ILOAD = 1A, l 3
Top Power NMOS Current Limit 3.5 4.8 5.8 A l 3
Bottom Power NMOS Current Limit 2.5 3.3 4.8 A VINTVCC = 3.4V 3
SW Leakage Current -1.5 1.5 µA VIN = 42V, VSW = 0V, 42V 3
EN/UV Pin Threshold (rising) 0.94 1 1.06 V EN/UV Rising, l 3
EN/UV Pin Current -20 20 nA VEN/UV = 2V 3
PG Upper Threshold Offset from VFB 6 9 12 % VFB Falling, l 3
PG Lower Threshold Offset from VFB -12 -9 -6 % VFB Rising, l 3
PG Leakage -40 40 nA VPG = 3.3V 3
PG Pull-Down Resistance 680 2000 Ω VPG = 0.1V, l 3
SYNC Threshold (falling) 0.8 1.1 1.4 V SYNC Falling 3
SYNC Threshold (rising) 1.6 2 2.4 V SYNC Rising 3
SYNC Pin Current -40 40 nA VSYNC = 2V 3
TR/SS Source Current 1.2 2.2 3.2 µA l 3
VIN, EN/UV, PG voltage 42 V 2
BIAS voltage 30 V 2
BST Pin Above SW Pin 4 V 2
FB, TR/SS, RT, INTVCC voltage 4 V 2
SYNC Voltage 6 V 2
Operating Junction Temperature Range -40 125 °C LT8610I 2
Storage Temperature Range -65 150 °C 2
Thermal Resistance, junction to ambient θJA 40 °C/W 2
Thermal Resistance, junction to case (exposed pad) θJC(PAD) 10 °C/W 2

CAD (KiCad official)

  • Symbol: LT8610IMSE#PBF
  • Footprint: Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm
  • 3D model: MSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lt8610imse-pbf-etched.step / lt8610imse-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt8610imse-pbf.step / lt8610imse-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 142ed1a2842742ea, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF