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LT8610EMSE#PBF

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Analog Devices DC-DC Converters, MSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT8610EMSE#PBF

Analog Devices · DC-DC Converters · MSOP-16-EP

LT8610EMSE#PBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input External clock synchronization input that must be grounded for Burst Mode operation, driven with 3V or higher or tied to INTVCC for pulse-skipping mode, and never left floating.
2 TR/SS bidirectional Output tracking and soft-start pin where a voltage below 0.97V forces FB to follow it, an internal 2.2µA pull-up from INTVCC sets the output ramp rate, and a 230Ω pull-down is active in shutdown and fault conditions.
3 RT passive A resistor from RT to ground sets the switching frequency.
4 EN/UV input Enable and undervoltage pin where the regulator shuts down when low and is active when high, with a 1.00V rising and 0.96V falling threshold, and it is tied to VIN if the shutdown feature is not used.
5 VIN power_in Input supply pin for internal circuitry and the top power switch, which must be tied to pin 6, locally bypassed, and rated to 42V absolute maximum.
6 VIN power_in Input supply pin for internal circuitry and the top power switch, which must be tied to pin 5, locally bypassed, and rated to 42V absolute maximum.
7 PGND power_in Power switch ground return for the internal bottom switch, which must be tied to pin 8 and connected close to the input capacitor negative terminal.
8 PGND power_in Power switch ground return for the internal bottom switch, which must be tied to pin 7 and connected close to the input capacitor negative terminal.
9 SW output Output of the internal power switches that must be tied together with pins 10 and 11 and connected to the inductor and boost capacitor, with the node kept small on the PCB.
10 SW output Output of the internal power switches that must be tied together with pins 9 and 11 and connected to the inductor and boost capacitor, with the node kept small on the PCB.
11 SW output Output of the internal power switches that must be tied together with pins 9 and 10 and connected to the inductor and boost capacitor, with the node kept small on the PCB.
12 BST power_out Provides a drive voltage above the input voltage to the top power switch, with a 0.1µF boost capacitor placed as close to the IC as possible and BST above SW limited to 4V.
13 INTVCC power_out Internal 3.4V regulator bypass pin that supplies at most 20mA, must not be loaded with external circuitry, and needs at least 1µF low ESR ceramic decoupling to power ground.
14 BIAS power_in Supply input that powers the internal regulator instead of VIN when tied above 3.1V, and it should be tied to VOUT for outputs of 3.3V and above, with a 1µF bypass if tied to another supply.
15 PG output Open-drain power-good output that stays low until FB is within ±9% of the regulation voltage with no fault present, and is valid when VIN is above 3.4V.
16 FB input Feedback input regulated to 0.970V, connected to the feedback divider tap, with a 4.7pF to 10pF phase lead capacitor connected between FB and VOUT.
17 GND power_in Exposed pad ground that must be connected to the negative terminal of the input capacitor and soldered to the PCB to lower thermal resistance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-16-EP
Category Power Management ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Minimum Input Voltage 2.9 3.4 V 2
VIN Quiescent Current 1 3 µA VEN/UV = 0V, VSYNC = 0V, 25°C 2
VIN Quiescent Current 1 8 µA VEN/UV = 0V, VSYNC = 0V, over operating temperature range 2
VIN Quiescent Current 1.7 4 µA VEN/UV = 2V, Not Switching, VSYNC = 0V, 25°C 2
VIN Quiescent Current 1.7 10 µA VEN/UV = 2V, Not Switching, VSYNC = 0V, over operating temperature range 2
VIN Quiescent Current 0.24 0.5 mA VEN/UV = 2V, Not Switching, VSYNC = 2V 2
VIN Current in Regulation 24 50 µA VOUT = 0.97V, VIN = 6V, Output Load = 100µA 2
VIN Current in Regulation 210 350 µA VOUT = 0.97V, VIN = 6V, Output Load = 1mA 2
Feedback Reference Voltage 0.964 0.97 0.976 V VIN = 6V, ILOAD = 0.5A, 25°C 2
Feedback Reference Voltage 0.958 0.97 0.982 V VIN = 6V, ILOAD = 0.5A, over operating temperature range 2
Feedback Voltage Line Regulation 0.004 0.02 %/V VIN = 4.0V to 42V, ILOAD = 0.5A 2
Feedback Pin Input Current -20 20 nA VFB = 1V 2
INTVCC Voltage 3.23 3.4 3.57 V ILOAD = 0mA, VBIAS = 0V 2
INTVCC Voltage 3.25 3.29 3.35 V ILOAD = 0mA, VBIAS = 3.3V 2
INTVCC Undervoltage Lockout 2.5 2.6 2.7 V 2
Minimum On-Time 30 50 70 ns ILOAD = 1A, SYNC = 0V 2
Minimum On-Time 30 45 65 ns ILOAD = 1A, SYNC = 3.3V 2
Minimum Off-Time 50 80 110 ns 2
BIAS Pin Current Consumption 8.5 mA VBIAS = 3.3V, ILOAD = 1A, 2MHz 2
Oscillator Frequency 180 210 240 kHz RT = 221k, ILOAD = 1A 3
Oscillator Frequency 665 700 735 kHz RT = 60.4k, ILOAD = 1A 3
Oscillator Frequency 1.85 2 2.15 MHz RT = 18.2k, ILOAD = 1A 3
Top Power NMOS On-Resistance 120 mΩ ISW = 1A 3
Top Power NMOS Current Limit 3.5 4.8 5.8 A 3
Bottom Power NMOS On-Resistance 65 mΩ VINTVCC = 3.4V, ISW = 1A 3
Bottom Power NMOS Current Limit 2.5 3.3 4.8 A VINTVCC = 3.4V 3
SW Leakage Current -1.5 1.5 µA VIN = 42V, VSW = 0V, 42V 3
EN/UV Pin Threshold 0.94 1 1.06 V EN/UV Rising 3
EN/UV Pin Hysteresis 40 mV 3
EN/UV Pin Current -20 20 nA VEN/UV = 2V 3
PG Upper Threshold Offset from VFB 6 9 12 % VFB Falling 3
PG Lower Threshold Offset from VFB -6 -9 -12 % VFB Rising 3
PG Hysteresis 1.3 % 3
PG Leakage -40 40 nA VPG = 3.3V 3
PG Pull-Down Resistance 680 2000 Ω VPG = 0.1V 3
SYNC Threshold (falling) 0.8 1.1 1.4 V SYNC Falling 3
SYNC Threshold (rising) 1.6 2 2.4 V SYNC Rising 3
SYNC Pin Current -40 40 nA VSYNC = 2V 3
TR/SS Source Current 1.2 2.2 3.2 µA 3
TR/SS Pull-Down Resistance 230 Ω Fault Condition, TR/SS = 0.1V 3
VIN, EN/UV, PG Maximum Voltage VIN, EN/UV, PG 42 V 2
BIAS Maximum Voltage BIAS 30 V 2
BST Pin Above SW Pin Maximum Voltage BST-SW 4 V 2
FB, TR/SS, RT, INTVCC Maximum Voltage FB, TR/SS, RT, INTVCC 4 V 2
SYNC Maximum Voltage SYNC 6 V 2
Operating Junction Temperature Range TJ -40 125 °C LT8610E (Note 2) 2
Storage Temperature Range TSTG -65 150 °C 2
INTVCC Maximum Output Current 20 mA 8
Thermal Resistance Junction-to-Ambient θJA 40 °C/W 2
Thermal Resistance Junction-to-Case (Exposed Pad) θJC(PAD) 10 °C/W 2

CAD (KiCad official)

  • Symbol: LT8610EMSE#PBF
  • Footprint: Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm
  • 3D model: MSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lt8610emse-pbf-etched.step / lt8610emse-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt8610emse-pbf.step / lt8610emse-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 142ed1a2842742ea, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF