component
LT8610AIMSE#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, MSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT8610AIMSE#TRPBF
Analog Devices · DC-DC Converters · MSOP-16-EP
LT8610AIMSE#TRPBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Ground this pin for low ripple Burst Mode operation at low loads, tie it to a clock source to synchronize to an external frequency, and apply a DC voltage of 3V or higher or tie it to INTVCC for pulse-skipping mode; do not float it. |
| 2 | TR/SS | bidirectional | A TR/SS voltage below 0.97V makes the regulator track FB to this pin, an internal 2.2µA pull-up from INTVCC sets the output ramp rate via a capacitor, and the pin is pulled to ground through an internal 230Ω MOSFET during shutdown and faults, so use a series resistor when driven from a low-impedance source. |
| 3 | RT | passive | A resistor tied between RT and ground sets the switching frequency. |
| 4 | EN/UV | input | The regulator is shut down when this pin is low and active when high, with a hysteretic threshold of 1.00V rising and 0.96V falling, and it must be tied to VIN if the shutdown feature is not used. |
| 5 | VIN | power_in | Supplies the internal circuitry and the internal top-side power switch; pins 5 and 6 must be tied together and locally bypassed with the input capacitor positive terminal placed close to these pins. |
| 6 | VIN | power_in | Supplies the internal circuitry and the internal top-side power switch; pins 5 and 6 must be tied together and locally bypassed with the input capacitor positive terminal placed close to these pins. |
| 7 | NC | unconnected | No connect; this pin is not connected to internal circuitry. |
| 8 | GND | power_in | Return path of the internal bottom-side switch that must be tied together with the other ground pins, placed close to the negative terminal of the input capacitor and the exposed pad. |
| 9 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 10 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 11 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 12 | BST | power_out | Provides a drive voltage higher than the input voltage to the top-side power switch and requires a 0.1µF boost capacitor placed as close as possible to the IC. |
| 13 | INTVCC | power_out | Internal 3.4V regulator bypass with a maximum output current of 20mA; do not load it externally and decouple it with at least a 1µF low ESR ceramic capacitor placed close to the IC. |
| 14 | BIAS | power_in | The internal regulator draws current from BIAS instead of VIN when BIAS is above 3.1V, and for output voltages of 3.3V and above it should be tied to VOUT (use a 1µF bypass if tied to another supply). |
| 15 | PG | output | Open-drain output that remains low until FB is within ±9% of the final regulation voltage with no fault conditions, and is valid when VIN is above 3.4V regardless of the EN/UV state. |
| 16 | FB | input | Regulates the FB pin to 0.970V; connect the feedback resistor divider tap here and a phase lead capacitor, typically 4.7pF to 10pF, between FB and VOUT. |
| 17 | GND | power_in | Exposed pad is ground and must be soldered to the PCB to lower the thermal resistance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Reference Voltage | VFB | 0.964 | 0.97 | 0.976 | V | VIN = 6V, ILOAD = 0.5A | 3 |
| Feedback Reference Voltage (full operating temperature range, l) | VFB | 0.958 | 0.97 | 0.982 | V | VIN = 6V, ILOAD = 0.5A; l = full operating temperature range | 3 |
| Feedback Voltage Line Regulation | 0.004 | 0.02 | %/V | VIN = 4V to 42V, ILOAD = 1A | 3 | ||
| Feedback Pin Input Current | -20 | 20 | nA | VFB = 1V | 3 | ||
| INTVCC Voltage | VINTVCC | 3.23 | 3.4 | 3.57 | V | ILOAD = 0mA, VBIAS = 0V | 3 |
| INTVCC Voltage | VINTVCC | 3.25 | 3.29 | 3.35 | V | ILOAD = 0mA, VBIAS = 3.3V | 3 |
| INTVCC Undervoltage Lockout | 2.5 | 2.6 | 2.7 | V | 3 | ||
| Minimum Input Voltage | 2.9 | 3.4 | V | (Note 4), l | 3 | ||
| VIN Quiescent Current | IQ | 1 | 3 | µA | VEN/UV = 0V, l | 3 | |
| VIN Quiescent Current | IQ | 1.7 | 4 | µA | VEN/UV = 2V, Not Switching, VSYNC = 0V, l | 3 | |
| VIN Quiescent Current | IQ | 0.26 | 0.5 | mA | VEN/UV = 2V, Not Switching, VSYNC = 2V | 3 | |
| VIN Current in Regulation | IIN | 24 | 50 | µA | VOUT = 0.97V, VIN = 6V, Output Load = 100µA (LT8610A), l | 3 | |
| VIN Current in Regulation | IIN | 210 | 350 | µA | VOUT = 0.97V, VIN = 6V, Output Load = 1mA (LT8610A), l | 3 | |
| Minimum On-Time | tON(MIN) | 15 | 30 | 45 | ns | ILOAD = 1A, SYNC = 0V, l | 3 |
| Minimum Off-Time | tOFF(MIN) | 95 | 125 | ns | 3 | ||
| Oscillator Frequency | fSW | 180 | 210 | 240 | kHz | RT = 221k, ILOAD = 1A, l | 4 |
| Oscillator Frequency | fSW | 665 | 700 | 735 | kHz | RT = 60.4k, ILOAD = 1A, l | 4 |
| Oscillator Frequency | fSW | 1.85 | 2 | 2.15 | MHz | RT = 18.2k, ILOAD = 1A, l | 4 |
| Top Power NMOS Current Limit | ILIM | 5 | 6.7 | 8 | A | LT8610A, l | 4 |
| Bottom Power NMOS Current Limit | ILIM | 3.4 | 4.3 | 5.4 | A | VINTVCC = 3.4V | 4 |
| SW Leakage Current | ISW | -1.5 | 1.5 | µA | VIN = 42V, VSW = 0V, 42V | 4 | |
| EN/UV Pin Threshold | VEN/UV | 0.94 | 1 | 1.06 | V | EN/UV Rising, l | 4 |
| EN/UV Pin Current | IEN/UV | -20 | 20 | nA | VEN/UV = 2V | 4 | |
| PG Upper Threshold Offset from VFB | 6 | 9 | 12 | % | VFB Falling, l | 4 | |
| PG Lower Threshold Offset from VFB | -12 | -9 | -6 | % | VFB Rising, l | 4 | |
| PG Leakage | -40 | 40 | nA | VPG = 3.3V | 4 | ||
| PG Pull-Down Resistance | 680 | 2000 | Ω | VPG = 0.1V, l | 4 | ||
| SYNC Threshold | VSYNC | 0.8 | 1.1 | 1.4 | V | SYNC Falling | 4 |
| SYNC Threshold | VSYNC | 1.6 | 2 | 2.4 | V | SYNC Rising | 4 |
| SYNC Pin Current | ISYNC | -40 | 40 | nA | VSYNC = 6V | 4 | |
| TR/SS Source Current | ITR/SS | 1 | 2 | 3.2 | µA | l | 4 |
| Top Power NMOS On-Resistance | RDS(ON) | 120 | mΩ | ISW = 1A | 4 | ||
| Bottom Power NMOS On-Resistance | RDS(ON) | 65 | mΩ | VINTVCC = 3.4V, ISW = 1A | 4 | ||
| EN/UV Pin Hysteresis | 40 | mV | 4 | ||||
| PG Hysteresis | 1.3 | % | 4 | ||||
| TR/SS Pull-Down Resistance | 230 | Ω | Fault Condition, TR/SS = 0.1V | 4 | |||
| BIAS Pin Current Consumption | IBIAS | 9 | mA | VBIAS = 3.3V, ILOAD = 1A, 2MHz | 3 | ||
| VIN, EN/UV, PG Voltage | VIN | 42 | V | 2 | |||
| BIAS Voltage | VBIAS | 30 | V | 2 | |||
| BST Pin Above SW Pin | VBST-SW | 4 | V | 2 | |||
| FB, TR/SS, RT, INTVCC Voltage | 4 | V | 2 | ||||
| VOUT, SYNC Voltage | 6 | V | 2 | ||||
| Operating Junction Temperature Range (LT8610AI) | TJ | -40 | 125 | °C | Note 2 | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Thermal Resistance, Junction to Ambient | θJA | 40 | °C/W | 16-Lead MSE package | 2 | ||
| Thermal Resistance, Junction to Case (Exposed Pad) | θJC(PAD) | 10 | °C/W | 16-Lead MSE package | 2 |
CAD (KiCad official)
- Symbol:
LT8610AIMSE#TRPBF - Footprint:
Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm - 3D model: MSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lt8610aimse-trpbf-etched.step/lt8610aimse-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8610aimse-trpbf.step/lt8610aimse-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
a7328de0512d031c, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT8610AIMSE#TRPBF
**Analog Devices** · DC-DC Converters · MSOP-16-EP
LT8610AIMSE#TRPBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Ground this pin for low ripple Burst Mode operation at low loads, tie it to a clock source to synchronize to an external frequency, and apply a DC voltage of 3V or higher or tie it to INTVCC for pulse-skipping mode; do not float it. |
| 2 | TR/SS | bidirectional | A TR/SS voltage below 0.97V makes the regulator track FB to this pin, an internal 2.2µA pull-up from INTVCC sets the output ramp rate via a capacitor, and the pin is pulled to ground through an internal 230Ω MOSFET during shutdown and faults, so use a series resistor when driven from a low-impedance source. |
| 3 | RT | passive | A resistor tied between RT and ground sets the switching frequency. |
| 4 | EN/UV | input | The regulator is shut down when this pin is low and active when high, with a hysteretic threshold of 1.00V rising and 0.96V falling, and it must be tied to VIN if the shutdown feature is not used. |
| 5 | VIN | power_in | Supplies the internal circuitry and the internal top-side power switch; pins 5 and 6 must be tied together and locally bypassed with the input capacitor positive terminal placed close to these pins. |
| 6 | VIN | power_in | Supplies the internal circuitry and the internal top-side power switch; pins 5 and 6 must be tied together and locally bypassed with the input capacitor positive terminal placed close to these pins. |
| 7 | NC | unconnected | No connect; this pin is not connected to internal circuitry. |
| 8 | GND | power_in | Return path of the internal bottom-side switch that must be tied together with the other ground pins, placed close to the negative terminal of the input capacitor and the exposed pad. |
| 9 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 10 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 11 | SW | power_out | Output of the internal power switches; pins 9, 10 and 11 must be tied together and connected to the inductor and boost capacitor, with the node kept small on the PCB. |
| 12 | BST | power_out | Provides a drive voltage higher than the input voltage to the top-side power switch and requires a 0.1µF boost capacitor placed as close as possible to the IC. |
| 13 | INTVCC | power_out | Internal 3.4V regulator bypass with a maximum output current of 20mA; do not load it externally and decouple it with at least a 1µF low ESR ceramic capacitor placed close to the IC. |
| 14 | BIAS | power_in | The internal regulator draws current from BIAS instead of VIN when BIAS is above 3.1V, and for output voltages of 3.3V and above it should be tied to VOUT (use a 1µF bypass if tied to another supply). |
| 15 | PG | output | Open-drain output that remains low until FB is within ±9% of the final regulation voltage with no fault conditions, and is valid when VIN is above 3.4V regardless of the EN/UV state. |
| 16 | FB | input | Regulates the FB pin to 0.970V; connect the feedback resistor divider tap here and a phase lead capacitor, typically 4.7pF to 10pF, between FB and VOUT. |
| 17 | GND | power_in | Exposed pad is ground and must be soldered to the PCB to lower the thermal resistance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Reference Voltage | VFB | 0.964 | 0.97 | 0.976 | V | VIN = 6V, ILOAD = 0.5A | 3 |
| Feedback Reference Voltage (full operating temperature range, l) | VFB | 0.958 | 0.97 | 0.982 | V | VIN = 6V, ILOAD = 0.5A; l = full operating temperature range | 3 |
| Feedback Voltage Line Regulation | | | 0.004 | 0.02 | %/V | VIN = 4V to 42V, ILOAD = 1A | 3 |
| Feedback Pin Input Current | | -20 | | 20 | nA | VFB = 1V | 3 |
| INTVCC Voltage | VINTVCC | 3.23 | 3.4 | 3.57 | V | ILOAD = 0mA, VBIAS = 0V | 3 |
| INTVCC Voltage | VINTVCC | 3.25 | 3.29 | 3.35 | V | ILOAD = 0mA, VBIAS = 3.3V | 3 |
| INTVCC Undervoltage Lockout | | 2.5 | 2.6 | 2.7 | V | | 3 |
| Minimum Input Voltage | | | 2.9 | 3.4 | V | (Note 4), l | 3 |
| VIN Quiescent Current | IQ | | 1 | 3 | µA | VEN/UV = 0V, l | 3 |
| VIN Quiescent Current | IQ | | 1.7 | 4 | µA | VEN/UV = 2V, Not Switching, VSYNC = 0V, l | 3 |
| VIN Quiescent Current | IQ | | 0.26 | 0.5 | mA | VEN/UV = 2V, Not Switching, VSYNC = 2V | 3 |
| VIN Current in Regulation | IIN | | 24 | 50 | µA | VOUT = 0.97V, VIN = 6V, Output Load = 100µA (LT8610A), l | 3 |
| VIN Current in Regulation | IIN | | 210 | 350 | µA | VOUT = 0.97V, VIN = 6V, Output Load = 1mA (LT8610A), l | 3 |
| Minimum On-Time | tON(MIN) | 15 | 30 | 45 | ns | ILOAD = 1A, SYNC = 0V, l | 3 |
| Minimum Off-Time | tOFF(MIN) | | 95 | 125 | ns | | 3 |
| Oscillator Frequency | fSW | 180 | 210 | 240 | kHz | RT = 221k, ILOAD = 1A, l | 4 |
| Oscillator Frequency | fSW | 665 | 700 | 735 | kHz | RT = 60.4k, ILOAD = 1A, l | 4 |
| Oscillator Frequency | fSW | 1.85 | 2 | 2.15 | MHz | RT = 18.2k, ILOAD = 1A, l | 4 |
| Top Power NMOS Current Limit | ILIM | 5 | 6.7 | 8 | A | LT8610A, l | 4 |
| Bottom Power NMOS Current Limit | ILIM | 3.4 | 4.3 | 5.4 | A | VINTVCC = 3.4V | 4 |
| SW Leakage Current | ISW | -1.5 | | 1.5 | µA | VIN = 42V, VSW = 0V, 42V | 4 |
| EN/UV Pin Threshold | VEN/UV | 0.94 | 1 | 1.06 | V | EN/UV Rising, l | 4 |
| EN/UV Pin Current | IEN/UV | -20 | | 20 | nA | VEN/UV = 2V | 4 |
| PG Upper Threshold Offset from VFB | | 6 | 9 | 12 | % | VFB Falling, l | 4 |
| PG Lower Threshold Offset from VFB | | -12 | -9 | -6 | % | VFB Rising, l | 4 |
| PG Leakage | | -40 | | 40 | nA | VPG = 3.3V | 4 |
| PG Pull-Down Resistance | | | 680 | 2000 | Ω | VPG = 0.1V, l | 4 |
| SYNC Threshold | VSYNC | 0.8 | 1.1 | 1.4 | V | SYNC Falling | 4 |
| SYNC Threshold | VSYNC | 1.6 | 2 | 2.4 | V | SYNC Rising | 4 |
| SYNC Pin Current | ISYNC | -40 | | 40 | nA | VSYNC = 6V | 4 |
| TR/SS Source Current | ITR/SS | 1 | 2 | 3.2 | µA | l | 4 |
| Top Power NMOS On-Resistance | RDS(ON) | | 120 | | mΩ | ISW = 1A | 4 |
| Bottom Power NMOS On-Resistance | RDS(ON) | | 65 | | mΩ | VINTVCC = 3.4V, ISW = 1A | 4 |
| EN/UV Pin Hysteresis | | | 40 | | mV | | 4 |
| PG Hysteresis | | | 1.3 | | % | | 4 |
| TR/SS Pull-Down Resistance | | | 230 | | Ω | Fault Condition, TR/SS = 0.1V | 4 |
| BIAS Pin Current Consumption | IBIAS | | 9 | | mA | VBIAS = 3.3V, ILOAD = 1A, 2MHz | 3 |
| VIN, EN/UV, PG Voltage | VIN | | | 42 | V | | 2 |
| BIAS Voltage | VBIAS | | | 30 | V | | 2 |
| BST Pin Above SW Pin | VBST-SW | | | 4 | V | | 2 |
| FB, TR/SS, RT, INTVCC Voltage | | | | 4 | V | | 2 |
| VOUT, SYNC Voltage | | | | 6 | V | | 2 |
| Operating Junction Temperature Range (LT8610AI) | TJ | -40 | | 125 | °C | Note 2 | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 2 |
| Thermal Resistance, Junction to Ambient | θJA | | 40 | | °C/W | 16-Lead MSE package | 2 |
| Thermal Resistance, Junction to Case (Exposed Pad) | θJC(PAD) | | 10 | | °C/W | 16-Lead MSE package | 2 |
## CAD (KiCad official)
- Symbol: `LT8610AIMSE#TRPBF`
- Footprint: `Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm`
- 3D model: MSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `lt8610aimse-trpbf-etched.step` / `lt8610aimse-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8610aimse-trpbf.step` / `lt8610aimse-trpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886349390745600) (26 pp, sha256 `a7328de0512d031c`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt8610aimse-trpbf-datasheet.pdf)