# LT8609AIMSE#PBF

**Analog Devices** · DC-DC Converters · MSOP-10-EP

LT8609AIMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Bootstrap capacitor pin providing the drive voltage (above VIN) for the internal top-side power NMOS switch. Place a 0.1µF ceramic capacitor from BST to SW as close to the IC as possible; do not place a series resistor. |
| 2 | SW | power_out | Switch node - output of the internal top-side and synchronous bottom-side power MOSFETs. Connect to the external inductor and to the bootstrap capacitor. Keep this node small on the PCB for good EMI/thermal performance. |
| 3 | INTVCC | power_out | Internal 3.5V LDO regulator bypass pin that supplies the internal gate drivers and control circuits. Voltage varies from 2.8V to 3.5V; max output 20mA. Decouple to GND with at least a 1µF low-ESR ceramic capacitor. Do not load with external circuitry. |
| 4 | RT | input | Oscillator frequency-set pin. Tie a resistor from RT to GND to program the switching frequency between 200kHz (RT = 221kΩ) and 2.2MHz (RT = 16.2kΩ). |
| 5 | SYNC | input | External clock synchronization / mode-select input. Tie to GND for low-ripple Burst Mode; drive with an external clock (200kHz-2.2MHz) to synchronize; leave floating for pulse-skipping mode; tie to INTVCC or 3.2V-5.0V for pulse-skipping mode with spread-spectrum modulation. |
| 6 | FB | input | Feedback input for the adjustable-output LT8609A. Regulated to 0.782V. Connect to the tap of the external VOUT-to-GND resistor divider that programs the output voltage. Add a ~10pF phase-lead capacitor from VOUT to FB when using large divider resistors. |
| 7 | TR/SS | input | Output tracking and soft-start pin. An internal 2µA pull-up from INTVCC charges an external capacitor to program the output-voltage slew rate. Below 0.782V the part regulates FB to the TR/SS voltage; above 0.782V tracking is disabled. Pulled to GND through a 300Ω MOSFET in shutdown and fault conditions. |
| 8 | PG | output | Power-good open-drain output. Held low until FB is within ±8.5% of the regulation setpoint and no fault is present. Absolute max 42V; valid when VIN > 3.2V regardless of EN/UV state. Requires an external pull-up resistor. |
| 9 | VIN | power_in | Main input supply pin, 3.0V to 42V. Supplies internal control circuitry and the internal top-side power switch. Locally bypass with a low-ESR ceramic capacitor placed close to VIN and the exposed-pad GND. |
| 10 | EN/UV | input | Enable / input under-voltage lockout pin. Rising threshold 1.05V, falling 1.00V. Ground to shut the part down (IQ ≈ 1µA); tie to VIN if shutdown/UVLO is not used, or use an external VIN divider to program a precise VIN turn-on threshold. Absolute max 42V. |
| 11 | GND | power_in | Exposed thermal pad - signal and power ground return. Must be soldered directly to the PCB ground plane both for the electrical return path and to achieve the specified θJA = 40°C/W thermal resistance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10-EP |
| Category | Power Management (PMIC) |
| Pins | 11 |

## Ordering variants

Same part, different packaging or reel option.

- `LT8609AIMSE#PBFEMSE`
- `LT8609AIMSE#PBF`
- `LT8609AIMSE#PBFHMSE`
- `LT8609AIMSE#PBFJMSE`
- `LT8609AIMSE#PBFEMSE16`
- `LT8609AIMSE16`
- `LT8609AIMSE#PBFHMSE16`
- `LT8609AIMSE#PBFJMSE16`
- `LT8609AIMSE#PBFEDDM`
- `LT8609AIMSE#PBFJDDM`
- `LT8609AIMSE#PBFHDDM`
- `LT8609AIMSE#PBFEDDM-3.3`
- `LT8609AIMSE#PBFJDDM-3.3`
- `LT8609AIMSE#PBFEDDM-5`
- `LT8609AIMSE#PBFJDDM-5`
- `LT8609AIMSE#PBFHDDM-5`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| FB, TR/SS pin voltage (absolute maximum) |  |  |  | 4 | V |  | 2 |
| SYNC pin voltage (absolute maximum) |  |  |  | 6 | V |  | 2 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 2 |
| Operating junction temperature range (LT8609AI grade) | TJ | -40 |  | 125 | °C | LT8609AI (MSE package, I grade) | 2 |
| Input voltage range (headline) | VIN | 3 |  | 42 | V | Stated in Features section, not in a table | 1 |
| Thermal resistance, junction to ambient (MSE package) | θJA |  | 40 |  | °C/W | 10-lead MSOP (MSE package) | 2 |
| Minimum Input Voltage |  | 2.7 | 3 | 3.2 | V |  | 4 |
| VIN Quiescent Current (not switching, EN/UV low) |  |  | 1 | 4 | µA | VEN/UV = 0V, VSYNC = 0V | 4 |
| VIN Quiescent Current (not switching, EN/UV high) |  |  | 1.7 | 12 | µA | VEN/UV = 2V, Not Switching, VSYNC = 0V | 4 |
| VIN Current in Regulation (100µA load) |  |  | 46 | 90 | µA | VIN = 6V, VOUT = 2.7V, Output Load = 100μA | 4 |
| VIN Current in Regulation (1mA load) |  |  | 480 | 700 | µA | VIN = 6V, VOUT = 2.7V, Output Load = 1mA | 4 |
| Feedback Reference Voltage (E-, I-, H-Grade) |  | 0.778 | 0.782 | 0.786 | V | VIN = 6V, ILOAD = 100mA | 4 |
| Feedback Reference Voltage (E-, I-, H-Grade, over temperature) |  | 0.77 | 0.782 | 0.794 | V | VIN = 6V, ILOAD = 100mA | 4 |
| Feedback Voltage Line Regulation |  |  | 0.004 | 0.02 | %/V | VIN = 4.0V to 40V | 4 |
| Feedback Pin Input Current |  | -20 |  | 20 | nA | VFB = 1.0V | 4 |
| Minimum On-Time |  |  | 45 | 75 | ns | ILOAD = 1.5A, SYNC = 0V | 4 |
| Minimum On-Time |  |  | 45 | 60 | ns | ILOAD = 1.5A, SYNC = 1.9V | 4 |
| Minimum Off Time |  |  | 90 | 130 | ns |  | 4 |
| Oscillator Frequency | RT | 155 | 200 | 245 | kHz | RT = 221k, ILOAD = 0.5A | 5 |
| Oscillator Frequency | RT | 640 | 700 | 760 | kHz | RT = 60.4k, ILOAD = 0.5A | 5 |
| Oscillator Frequency | RT | 1.925 | 2 | 2.075 | MHz | RT = 18.2k, ILOAD = 0.5A | 5 |
| Top Power NMOS Current Limit |  | 3.4 | 4.5 | 5.7 | A |  | 5 |
| SW Leakage Current |  |  |  | 15 | µA | VIN = 42V, VSW = 40V | 5 |
| EN/UV Pin Threshold (rising) |  | 0.99 | 1.05 | 1.11 | V | EN/UV Rising | 5 |
| EN/UV Pin Current (LT8609/LT8609A) |  | -20 |  | 20 | nA | VEN/UV = 2V | 5 |
| PG Upper Threshold Offset from VFB (LT8609/LT8609A) |  | 5 | 8.5 | 13 | % | VFB Rising | 5 |
| PG Lower Threshold Offset from VFB (LT8609/LT8609A) |  | 5 | 8.5 | 13 | % | VFB Falling | 5 |
| PG Leakage Current | VPG | -200 |  | 200 | nA | VPG = 42V | 5 |
| PG Pull-Down Resistance |  |  | 550 | 1200 | Ω | VPG = 0.1V | 5 |
| Sync Low Input Voltage (LT8609/LT8609A) |  | 0.4 |  | 0.9 | V |  | 5 |
| Sync High Input Voltage (LT8609/LT8609A) |  | 2.7 |  | 3.2 | V | INTVCC = 3.5V | 5 |
| TR/SS Source Current |  | 1 | 2 | 3 | µA |  | 5 |
| TR/SS Pull-Down Resistance |  |  | 300 | 900 | Ω | Fault Condition, TR/SS = 0.1V | 5 |
| Spread Spectrum Modulation Frequency (LT8609/LT8609A) | VSYNC | 1 | 3 | 6 | kHz | VSYNC = 3.3V | 5 |

## CAD (KiCad official)

- Symbol: `LT8609AIMSE#PBF`
- Footprint: `Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm`
- 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files: `lt8609aimse-pbf-etched.step` / `lt8609aimse-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8609aimse-pbf.step` / `lt8609aimse-pbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836534217682944) (30 pp, sha256 `bb514bf594e97238`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lt8609aimse-pbf-datasheet.pdf)