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LT8471EFE#TRPBF
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Analog Devices DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LT8471EFE#TRPBF
Analog Devices · DC-DC Converters · HTSSOP-20-EP
LT8471EFE#TRPBF from Analog Devices, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | C1 | output | Collector of the primary channel 1 internal NPN power switch; if tied to a DC voltage it must be locally bypassed, and if it is a switching pin its trace area must be minimized to reduce EMI. |
| 2 | E1 | passive | Emitter of the primary channel 1 internal NPN power switch; unless grounded, its trace area must be minimized to reduce EMI. |
| 3 | VIN1 | power_in | Input supply 1 for primary channel 1 and the Skyhook channel, which also powers common circuitry; VIN1 must be greater than 2.6V for any channel to operate and must be locally bypassed. |
| 4 | PG1 | output | Open-drain power-good output for channel 1 that is pulled low when the output is more than 7.5% below target and released when the output is above 92.5% of target, requiring an external pull-up resistor. |
| 5 | FB1 | input | Feedback pin for primary channel 1, where a resistor divider between VOUT, FB and GND sets the output voltage. |
| 6 | OV/UV | input | Overvoltage/undervoltage pin that must be tied to 1.215V (typical) or more to enable the device and grounded to shut down, and can be configured as UVLO and OVLO through an external resistor divider. |
| 7 | RT | passive | Timing resistor pin that sets the free-running switching frequency through a resistor to ground and must not be left floating. |
| 8 | SS1 | passive | Soft-start pin for channel 1 that takes a soft-start capacitor and is charged nominally through 250k to about 2.15V at start-up. |
| 9 | SYNC | input | Synchronization input that accepts an external clock with a high level above 1.3V and a low level below 0.4V, and reverts to the internal free-running clock when driven below 0.4V. |
| 10 | GND | power_in | Ground pin that must be soldered directly to the local ground plane. |
| 11 | GND | power_in | Ground pin that must be soldered directly to the local ground plane. |
| 12 | GND | power_in | Ground pin that must be soldered directly to the local ground plane. |
| 13 | C3 | output | Collector of the Skyhook channel internal NPN power switch; if the Skyhook channel is not used this pin must be tied to GND, and if used its metal trace area must be minimized to reduce EMI. |
| 14 | SHOUT | output | Skyhook output voltage pin that is the cathode of the internal Schottky diode and the output of the Skyhook boost converter. |
| 15 | SS2 | passive | Soft-start pin for channel 2 that takes a soft-start capacitor and is charged nominally through 250k to about 2.15V at start-up. |
| 16 | FB2 | input | Feedback pin for primary channel 2, where a resistor divider between VOUT, FB and GND sets the output voltage. |
| 17 | PG2 | output | Open-drain power-good output for channel 2 that is pulled low when the output is more than 7.5% below target and released when the output is above 92.5% of target, requiring an external pull-up resistor. |
| 18 | VIN2 | power_in | Input supply 2 for primary channel 2 that must be greater than 2.6V when channel 2 is in use and must be locally bypassed. |
| 19 | E2 | passive | Emitter of the primary channel 2 internal NPN power switch; unless grounded, its trace area must be minimized to reduce EMI. |
| 20 | C2 | output | Collector of the primary channel 2 internal NPN power switch that must be tied to the Skyhook channel input voltage when the Skyhook channel is used, and must be bypassed or have its trace minimized as for C1. |
| 21 | GND | power_in | Exposed pad that is ground, must be soldered to the PCB, and provides both electrical contact to ground and thermal contact to the board. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage (VIN1, VIN2) | 2.6 | 50 | V | 3 | |||
| Quiescent Current (VIN1, Skyhook Disabled) | 2.2 | 3.3 | mA | VOV/UV = 1.3V, Not Switching | 3 | ||
| Quiescent Current (VIN1, Skyhook Enabled) | 2.4 | 4 | mA | VOV/UV = 1.3V, C3 = 5V, Not Switching | 3 | ||
| Quiescent Current (VIN2) | 29 | 42 | µA | VOV/UV = 1.3V, Not Switching | 3 | ||
| Quiescent Current in Shutdown (VIN1 + VIN2) | 0.01 | 1 | μA | VOV/UV = 0V | 3 | ||
| Positive Feedback Voltage (FB1, FB2) | 773 | 789 | 805 | mV | 3 | ||
| Negative Feedback Voltage (FB1, FB2) | -806 | -788 | -770 | mV | LT8471E,I | 3 | |
| Feedback Pin Bias Current (FB1, FB2) | -100 | 30 | 200 | nA | VFB = Positive Feedback Voltage, Current Out of Pin | 3 | |
| Feedback Pin Bias Current (FB1, FB2) | 0 | 100 | nA | VFB = Negative Feedback Voltage | 3 | ||
| Reference Line Regulation | 0.008 | 0.05 | %/V | 2.6V ≤ VIN1 ≤ 50V | 3 | ||
| Switching Frequency, fOSC | fOSC | 1.55 | 1.8 | 2.05 | MHz | RT = 46.4k | 3 |
| Switching Frequency, fOSC | fOSC | 100 | 117 | 135 | kHz | RT = 732k | 3 |
| Switching Frequency Range Synchronizing | 100 | 2000 | kHz | 3 | |||
| SYNC High Level for Sync | 1.3 | V | 3 | ||||
| SYNC Low Level for Sync | 0.4 | V | 3 | ||||
| SYNC Clock Pulse Duty Cycle | 35 | 65 | % | VSYNC = 0V to 2V | 3 | ||
| Switching Phase Between Primary Channels | 170 | 200 | Deg | RT = 46.4k | 3 | ||
| Skyhook Boost Voltage | VSHOUT, VC2 | 3 | 4.25 | 5.4 | V | VSHOUT, VC2, Skyhook Enabled | 3 |
| Switch Current Limit (Primary Channels) | 2.1 | 2.55 | 3.2 | A | Minimum Duty Cycle (Note 3) | 4 | |
| Switch Current Limit (Primary Channels) | 1.35 | 1.8 | 2.5 | A | Maximum Duty Cycle (Notes 3, 4) | 4 | |
| Switch Current Limit (Skyhook) | 400 | 500 | 600 | mA | (Note 3) | 4 | |
| C1, C2 Leakage Current | 0.01 | 1 | µA | VC1 = VC2 = 12V, VE1 = VE2 = 0V, VOV/UV = 0V, Current into Pin | 4 | ||
| C3 Leakage Current | 0.01 | 1 | µA | VC3 = 12V, VOV/UV = 0V | 4 | ||
| E1, E2 Leakage Current | 0.01 | 1 | µA | VOV/UV = 0V, Current Out of Pin, VC1 = VC2 = 20V, VE1 = VE2 = 5V | 4 | ||
| Schottky Reverse Leakage | VREVERSE | 0.01 | 1 | µA | VREVERSE = 12V | 4 | |
| Schottky Reverse Leakage | VREVERSE | 0.02 | 2 | µA | VREVERSE = 50V | 4 | |
| Soft-Start Charge Current | 5.5 | 8.5 | 11.5 | µA | VSS1, VSS2 = 50mV, Current Flows Out of SS1, SS2 Pins | 4 | |
| OV/UV Current for OVLO | 76 | 80 | 84 | µA | Current into OV/UV Pin. VOV/UV Internally Clamped to 1.37V, Current Rising | 4 | |
| OV/UV Pin Bias Current | 0.01 | 0.5 | µA | VOV/UV =1V | 4 | ||
| OV/UV Minimum Input Voltage High | 1.165 | 1.215 | 1.265 | V | Active Mode, OV/UV Rising | 4 | |
| OV/UV Minimum Input Voltage Low | 1.13 | 1.18 | 1.22 | V | Active Mode, OV/UV Falling | 4 | |
| OV/UV Input Voltage Low | 0.3 | V | Shutdown Mode | 4 | |||
| FB Pin Threshold for Power Good (Positive Output Voltage) | 715 | 740 | 765 | mV | FB Rising | 4 | |
| FB Pin Threshold for Power Good (Positive Output Voltage) | 708 | 730 | 752 | mV | FB Falling | 4 | |
| FB Pin Threshold for Power Good (Negative Output Voltage) | -766 | -736 | -706 | mV | FB Falling | 4 | |
| FB Pin Threshold for Power Good (Negative Output Voltage) | -755 | -727 | -699 | mV | FB Rising | 4 | |
| PG1, PG2 Voltage Output Low | 0.32 | 0.6 | V | VFB = 0.6V, IPG = 250μA | 4 | ||
| PG1, PG2 Leakage | 0.01 | 1 | µA | VPG1, VPG2 = 12V, PG Driver Off | 4 | ||
| VIN1, VIN2 Voltages | -0.3 | 50 | V | 2 | |||
| C1, C2 Voltages | -0.4 | 50 | V | 2 | |||
| E1, E2 Voltages | -60 | 50 | V | 2 | |||
| VC1 to VE1 and VC2 to VE2 Voltages | -0.4 | 60 | V | 2 | |||
| VIN1 to VE1 and VIN2 to VE2 Voltages | -0.4 | 40 | V | Low Side Configurations (Note 6) | 2 | ||
| VIN1 to VE1 and VIN2 to VE2 Voltages | -0.4 | 60 | V | High Side Configurations (Note 6) | 2 | ||
| VIN1 to VC1 and VIN2 to VC2 Voltages | -0.4 | 40 | V | High Side Configurations (Note 6) | 2 | ||
| C3 Voltage | -0.4 | 50 | V | 2 | |||
| RT Voltage | -0.3 | 5 | V | 2 | |||
| SYNC Voltage | -0.3 | 5.5 | V | 2 | |||
| SS1, SS2 | -0.3 | 2.5 | V | 2 | |||
| FB1, FB2 Voltages | -2.5 | 2.5 | V | 2 | |||
| PG1, PG2 Voltages | -0.3 | 50 | V | 2 | |||
| OV/UV Voltage | -0.3 | 5 | V | 2 | |||
| SHOUT Voltage | -0.3 | 50 | V | 2 | |||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | LT8471E (Notes 2, 5) | 2 | |
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Thermal Resistance, Junction to Ambient | θJA | 38 | °C/W | FE package, 20-lead TSSOP | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | switching pins small. Board layout also has a significant effect on thermal resistance. The exposed package ground pad is the copper | 25 |
CAD (KiCad official)
- Symbol:
LT8471EFE#TRPBF - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lt8471efe-trpbf-etched.step/lt8471efe-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8471efe-trpbf.step/lt8471efe-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
245eb55e0302d439, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).