component
LT8390EFE#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT8390EFE#TRPBF
Analog Devices · DC-DC Converters · HTSSOP-28
LT8390EFE#TRPBF from Analog Devices, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BG1 | output | Buck side bottom N-channel MOSFET gate drive, swinging from ground to INTVCC. |
| 2 | BST1 | power_out | Buck side bootstrap floating driver supply with an integrated Schottky diode from INTVCC, requiring an external bootstrap capacitor to SW1 and swinging from a diode drop below INTVCC to (VIN + INTVCC). |
| 3 | SW1 | output | Buck side switch node that swings from a Schottky diode drop below ground up to VIN. |
| 4 | TG1 | output | Buck side top N-channel MOSFET gate drive, swinging from SW1 to BST1. |
| 5 | LSP | passive | Positive terminal of the buck side inductor current sense resistor (RSENSE), requiring a Kelvin connection for accurate current sensing. |
| 6 | LSN | passive | Negative terminal of the buck side inductor current sense resistor (RSENSE), requiring a Kelvin connection for accurate current sensing. |
| 7 | VIN | power_in | Input supply that must be tied to the power input to set buck, buck-boost or boost regions, bypassed locally with a minimum 1µF ceramic capacitor. |
| 8 | INTVCC | power_out | Internal 5V linear regulator output, supplied from VIN, powering control circuitry and gate drivers and bypassed with a minimum 4.7µF ceramic capacitor. |
| 9 | EN/UVLO | input | Enable and undervoltage lockout: forcing below 0.3V shuts the part down, above 1.233V gives normal operation, and the 1.220V falling threshold sets UVLO via a resistor divider; tie directly to VIN if unused. |
| 10 | TEST | input | Factory test pin for testing only, which must be directly connected to ground for the part to operate properly. |
| 11 | LOADEN | input | Load switch enable input for the high side PMOS load switch; tie to VREF or INTVCC if unused, and forcing it low turns off TG1 and TG2, turns on BG1 and BG2, and turns off LOADTG. |
| 12 | VREF | power_out | Voltage reference output providing an accurate 2V reference capable of supplying 1mA, bypassed with a 0.47µF ceramic capacitor. |
| 13 | CTRL | input | Control input that programs the ISP/ISN current sense threshold from VREF or a resistor divider; forcing it below 0.3V stops switching, and tying it to VREF gives the 100mV full scale threshold. |
| 14 | ISP | input | Positive terminal of the ISP/ISN current sense resistor (RIS), requiring a Kelvin connection for accurate current sensing. |
| 15 | ISN | input | Negative terminal of the ISP/ISN current sense resistor (RIS), requiring a Kelvin connection for accurate current sensing. |
| 16 | ISMON | output | ISP/ISN current sense monitor output equal to ten times V(ISP-ISN) plus a 0.25V offset, and tied from master ISMON to slave CTRL in parallel applications. |
| 17 | PGOOD | output | Open-drain power good output that is pulled low when FB is within ±10% of the final regulation voltage and requires an external pull-up resistor. |
| 18 | SS | passive | Soft-start timer pin with a 12.5µA internal pull-up, where a 0.1µF capacitor is recommended and a resistor to VREF selects hiccup, latch-off (499kΩ) or keep-running (100kΩ) short-circuit fault mode. |
| 19 | FB | input | Voltage loop feedback input that regulates to 1.00V, where VFB below 0.25V triggers the short-circuit fault mode and VFB above 1.1V turns off TG1, BG1, TG2, BG2 and LOADTG. |
| 20 | VC | passive | Error amplifier output that sets the inductor current comparator threshold and is compensated with an external RC network. |
| 21 | RT | passive | Switching frequency setting pin, where a resistor to ground sets the internal oscillator frequency from 150kHz to 650kHz. |
| 22 | SYNC/SPRD | input | Grounded for internal oscillator frequency, driven by a clock for external synchronization, or tied to INTVCC for ±15% triangle spread spectrum. |
| 23 | LOADTG | output | High side PMOS load switch top gate drive, a buffered inverted LOADEN signal swinging from the higher of (VOUT-5V) and 1.2V up to VOUT, left unconnected if not used. |
| 24 | VOUT | power_in | Output supply that must be tied to the power output to set buck, buck-boost or boost regions and serves as the positive rail for LOADTG, bypassed with a minimum 1µF ceramic capacitor. |
| 25 | TG2 | output | Boost side top N-channel MOSFET gate drive, swinging from SW2 to BST2. |
| 26 | SW2 | output | Boost side switch node that swings from a Schottky diode drop below ground up to VOUT. |
| 27 | BST2 | power_out | Boost side bootstrap floating driver supply with an integrated Schottky diode from INTVCC, requiring an external bootstrap capacitor to SW2 and swinging from a diode drop below INTVCC to (VOUT + INTVCC). |
| 28 | BG2 | output | Boost side bottom N-channel MOSFET gate drive, swinging from ground to INTVCC. |
| 29 | GND | power_in | Exposed pad ground that must be soldered directly to the ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | HTSSOP-28 |
| Category | Power Management (PMIC) |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, EN/UVLO, VOUT, ISP, ISN voltage | VIN | 60 | V | 2 | |||
| (ISP-ISN) differential voltage | ISP-ISN | -1 | 1 | V | 2 | ||
| SW1, SW2, LSP, LSN voltage | SW1 | -6 | 60 | V | 2 | ||
| INTVCC, (BST1-SW1), (BST2-SW2) voltage | INTVCC | 6 | V | 2 | |||
| (BST1-LSP), (BST1-LSN) voltage | BST1-LSP | 6 | V | 2 | |||
| FB, LOADEN, SYNC/SPRD, CTRL, PGOOD voltage | FB | 6 | V | 2 | |||
| Operating junction temperature range, LT8390E | TJ | -40 | 125 | °C | LT8390E grade | 2 | |
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| VIN Operating Voltage Range | 4 | 60 | V | 3 | |||
| VIN Quiescent Current | 1 | 2 | µA | VEN/UVLO = 0.3V | 3 | ||
| VIN Quiescent Current, not switching | 2.1 | 2.8 | mA | Not Switching | 3 | ||
| INTVCC Regulation Voltage | 4.85 | 5 | 5.15 | V | IINTVCC = 20mA | 3 | |
| INTVCC Current Limit | 80 | 110 | 160 | mA | VINTVCC = 4.5V | 3 | |
| INTVCC Undervoltage Lockout Threshold | 3.44 | 3.54 | 3.64 | V | Falling | 3 | |
| VREF Regulation Voltage | 1.97 | 2 | 2.03 | V | IVREF = 100µA | 3 | |
| VREF Undervoltage Lockout Threshold | 1.78 | 1.84 | 1.9 | V | Falling | 3 | |
| EN/UVLO Shutdown Threshold | 0.3 | 0.6 | 1 | V | 3 | ||
| EN/UVLO Enable Threshold | 1.196 | 1.22 | 1.244 | V | Falling | 3 | |
| CTRL Input Bias Current | 0 | 20 | 50 | nA | VCTRL = 0.75V, current out of pin | 3 | |
| CTRL Latch-Off Threshold | 285 | 300 | 315 | mV | Falling | 3 | |
| LOADEN Threshold | 1.3 | 1.4 | 1.5 | V | Rising | 3 | |
| Minimum VOUT for LOADTG to be On | 2.4 | 3 | V | VLOADEN = 5V | 3 | ||
| LOADTG On Voltage V(VOUT-LOADTG) | 4.6 | 5 | 5.4 | V | VOUT = 12V | 3 | |
| LOADTG Off Voltage V(VOUT-LOADTG) | -0.1 | 0 | 0.1 | V | VOUT = 12V | 3 | |
| Full Scale Current Regulation V(ISP-ISN) | 97 | 100 | 103 | mV | VCTRL = 2V, VISP = 12V | 4 | |
| ISMON Monitor Output VISMON | VISMON | 1.2 | 1.25 | 1.3 | V | V(ISP-ISN) = 100mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output VISMON | VISMON | 0.3 | 0.35 | 0.4 | V | V(ISP-ISN) = 10mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output VISMON | VISMON | 0.2 | 0.25 | 0.3 | V | V(ISP-ISN) = 0mV, VISP = 12V/0V | 4 |
| ISP/ISN Input Common Mode Range | 0 | 60 | V | 4 | |||
| FB Regulation Voltage | 0.985 | 1 | 1.015 | V | VC = 1.2V | 4 | |
| Maximum Current Sense Threshold V(LSP-LSN), Buck | 35 | 50 | 65 | mV | Buck, VFB = 0.8V | 4 | |
| Maximum Current Sense Threshold V(LSP-LSN), Boost | 40 | 50 | 60 | mV | Boost, VFB = 0.8V | 4 | |
| FB Overvoltage Threshold (VFB) | VFB | 1.08 | 1.1 | 1.12 | V | Rising | 4 |
| FB Overvoltage Hysteresis | 35 | 50 | 65 | mV | 4 | ||
| FB Short Threshold (VFB) | VFB | 0.24 | 0.25 | 0.26 | V | Falling | 4 |
| FB Short Hysteresis | 35 | 50 | 65 | mV | 4 | ||
| PGOOD Upper Threshold Offset from VFB | 8 | 10 | 12 | % | Rising | 4 | |
| PGOOD Lower Threshold Offset from VFB | -12 | -10 | -8 | % | Falling | 4 | |
| SS Pull-Up Current | 10.5 | 12.5 | 14.5 | µA | VFB = 0.4V, VSS = 0V | 4 | |
| Switching Frequency | 190 | 200 | 210 | kHz | VSYNC/SPRD = 0V, RT = 226kΩ | 5 | |
| Switching Frequency | 380 | 400 | 420 | kHz | VSYNC/SPRD = 0V, RT = 100kΩ | 5 | |
| Switching Frequency | 570 | 600 | 630 | kHz | VSYNC/SPRD = 0V, RT = 59.0kΩ | 5 | |
| SYNC Frequency | 150 | 650 | kHz | 5 | |||
| Highest Spread Spectrum Above Oscillator Frequency | 12.5 | 14.5 | 16.5 | % | VSYNC/SPRD = 5V | 5 | |
| Lowest Spread Spectrum Below Oscillator Frequency | -17.7 | -15.7 | -13.7 | % | VSYNC/SPRD = 5V | 5 | |
| Buck-Boost to Boost region transition | VIN/VOUT | 0.73 | 0.75 | 0.77 | 5 | ||
| Boost to Buck-Boost region transition | VIN/VOUT | 0.83 | 0.85 | 0.87 | 5 | ||
| Buck to Buck-Boost region transition | VIN/VOUT | 1.16 | 1.18 | 1.2 | 5 | ||
| Buck-Boost to Buck region transition | VIN/VOUT | 1.31 | 1.33 | 1.35 | 5 | ||
| Peak-Buck to Peak-Boost transition | VIN/VOUT | 0.96 | 0.98 | 1 | 5 | ||
| Peak-Boost to Peak-Buck transition | VIN/VOUT | 1 | 1.02 | 1.04 | 5 | ||
| TG1 Minimum Duty Cycle in Buck Region | 10 | % | Peak-Buck Current Mode | 5 | |||
| TG1 Maximum Duty Cycle in Buck Region | 95 | % | Peak-Buck Current Mode | 5 | |||
| BG2 Minimum Duty Cycle in Boost Region | 10 | % | Peak-Boost Current Mode | 5 | |||
| BG2 Maximum Duty Cycle in Boost Region | 95 | % | Peak-Boost Current Mode | 5 | |||
| Thermal resistance, junction-to-ambient (FE package) | θJA | 30 | °C/W | 28-lead plastic TSSOP (FE package) | 2 | ||
| Thermal resistance, junction-to-case (FE package) | θJC | 5 | °C/W | 28-lead plastic TSSOP (FE package) | 2 |
CAD (KiCad official)
- Symbol:
LT8390EFE#TRPBF - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files:
lt8390efe-trpbf-etched.step/lt8390efe-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8390efe-trpbf.step/lt8390efe-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
b28ebec4c561175d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT8390EFE#TRPBF
**Analog Devices** · DC-DC Converters · HTSSOP-28
LT8390EFE#TRPBF from Analog Devices, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BG1 | output | Buck side bottom N-channel MOSFET gate drive, swinging from ground to INTVCC. |
| 2 | BST1 | power_out | Buck side bootstrap floating driver supply with an integrated Schottky diode from INTVCC, requiring an external bootstrap capacitor to SW1 and swinging from a diode drop below INTVCC to (VIN + INTVCC). |
| 3 | SW1 | output | Buck side switch node that swings from a Schottky diode drop below ground up to VIN. |
| 4 | TG1 | output | Buck side top N-channel MOSFET gate drive, swinging from SW1 to BST1. |
| 5 | LSP | passive | Positive terminal of the buck side inductor current sense resistor (RSENSE), requiring a Kelvin connection for accurate current sensing. |
| 6 | LSN | passive | Negative terminal of the buck side inductor current sense resistor (RSENSE), requiring a Kelvin connection for accurate current sensing. |
| 7 | VIN | power_in | Input supply that must be tied to the power input to set buck, buck-boost or boost regions, bypassed locally with a minimum 1µF ceramic capacitor. |
| 8 | INTVCC | power_out | Internal 5V linear regulator output, supplied from VIN, powering control circuitry and gate drivers and bypassed with a minimum 4.7µF ceramic capacitor. |
| 9 | EN/UVLO | input | Enable and undervoltage lockout: forcing below 0.3V shuts the part down, above 1.233V gives normal operation, and the 1.220V falling threshold sets UVLO via a resistor divider; tie directly to VIN if unused. |
| 10 | TEST | input | Factory test pin for testing only, which must be directly connected to ground for the part to operate properly. |
| 11 | LOADEN | input | Load switch enable input for the high side PMOS load switch; tie to VREF or INTVCC if unused, and forcing it low turns off TG1 and TG2, turns on BG1 and BG2, and turns off LOADTG. |
| 12 | VREF | power_out | Voltage reference output providing an accurate 2V reference capable of supplying 1mA, bypassed with a 0.47µF ceramic capacitor. |
| 13 | CTRL | input | Control input that programs the ISP/ISN current sense threshold from VREF or a resistor divider; forcing it below 0.3V stops switching, and tying it to VREF gives the 100mV full scale threshold. |
| 14 | ISP | input | Positive terminal of the ISP/ISN current sense resistor (RIS), requiring a Kelvin connection for accurate current sensing. |
| 15 | ISN | input | Negative terminal of the ISP/ISN current sense resistor (RIS), requiring a Kelvin connection for accurate current sensing. |
| 16 | ISMON | output | ISP/ISN current sense monitor output equal to ten times V(ISP-ISN) plus a 0.25V offset, and tied from master ISMON to slave CTRL in parallel applications. |
| 17 | PGOOD | output | Open-drain power good output that is pulled low when FB is within ±10% of the final regulation voltage and requires an external pull-up resistor. |
| 18 | SS | passive | Soft-start timer pin with a 12.5µA internal pull-up, where a 0.1µF capacitor is recommended and a resistor to VREF selects hiccup, latch-off (499kΩ) or keep-running (100kΩ) short-circuit fault mode. |
| 19 | FB | input | Voltage loop feedback input that regulates to 1.00V, where VFB below 0.25V triggers the short-circuit fault mode and VFB above 1.1V turns off TG1, BG1, TG2, BG2 and LOADTG. |
| 20 | VC | passive | Error amplifier output that sets the inductor current comparator threshold and is compensated with an external RC network. |
| 21 | RT | passive | Switching frequency setting pin, where a resistor to ground sets the internal oscillator frequency from 150kHz to 650kHz. |
| 22 | SYNC/SPRD | input | Grounded for internal oscillator frequency, driven by a clock for external synchronization, or tied to INTVCC for ±15% triangle spread spectrum. |
| 23 | LOADTG | output | High side PMOS load switch top gate drive, a buffered inverted LOADEN signal swinging from the higher of (VOUT-5V) and 1.2V up to VOUT, left unconnected if not used. |
| 24 | VOUT | power_in | Output supply that must be tied to the power output to set buck, buck-boost or boost regions and serves as the positive rail for LOADTG, bypassed with a minimum 1µF ceramic capacitor. |
| 25 | TG2 | output | Boost side top N-channel MOSFET gate drive, swinging from SW2 to BST2. |
| 26 | SW2 | output | Boost side switch node that swings from a Schottky diode drop below ground up to VOUT. |
| 27 | BST2 | power_out | Boost side bootstrap floating driver supply with an integrated Schottky diode from INTVCC, requiring an external bootstrap capacitor to SW2 and swinging from a diode drop below INTVCC to (VOUT + INTVCC). |
| 28 | BG2 | output | Boost side bottom N-channel MOSFET gate drive, swinging from ground to INTVCC. |
| 29 | GND | power_in | Exposed pad ground that must be soldered directly to the ground plane. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | HTSSOP-28 |
| Category | Power Management (PMIC) |
| Pins | 29 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, EN/UVLO, VOUT, ISP, ISN voltage | VIN | | | 60 | V | | 2 |
| (ISP-ISN) differential voltage | ISP-ISN | -1 | | 1 | V | | 2 |
| SW1, SW2, LSP, LSN voltage | SW1 | -6 | | 60 | V | | 2 |
| INTVCC, (BST1-SW1), (BST2-SW2) voltage | INTVCC | | | 6 | V | | 2 |
| (BST1-LSP), (BST1-LSN) voltage | BST1-LSP | | | 6 | V | | 2 |
| FB, LOADEN, SYNC/SPRD, CTRL, PGOOD voltage | FB | | | 6 | V | | 2 |
| Operating junction temperature range, LT8390E | TJ | -40 | | 125 | °C | LT8390E grade | 2 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 2 |
| VIN Operating Voltage Range | | 4 | | 60 | V | | 3 |
| VIN Quiescent Current | | | 1 | 2 | µA | VEN/UVLO = 0.3V | 3 |
| VIN Quiescent Current, not switching | | | 2.1 | 2.8 | mA | Not Switching | 3 |
| INTVCC Regulation Voltage | | 4.85 | 5 | 5.15 | V | IINTVCC = 20mA | 3 |
| INTVCC Current Limit | | 80 | 110 | 160 | mA | VINTVCC = 4.5V | 3 |
| INTVCC Undervoltage Lockout Threshold | | 3.44 | 3.54 | 3.64 | V | Falling | 3 |
| VREF Regulation Voltage | | 1.97 | 2 | 2.03 | V | IVREF = 100µA | 3 |
| VREF Undervoltage Lockout Threshold | | 1.78 | 1.84 | 1.9 | V | Falling | 3 |
| EN/UVLO Shutdown Threshold | | 0.3 | 0.6 | 1 | V | | 3 |
| EN/UVLO Enable Threshold | | 1.196 | 1.22 | 1.244 | V | Falling | 3 |
| CTRL Input Bias Current | | 0 | 20 | 50 | nA | VCTRL = 0.75V, current out of pin | 3 |
| CTRL Latch-Off Threshold | | 285 | 300 | 315 | mV | Falling | 3 |
| LOADEN Threshold | | 1.3 | 1.4 | 1.5 | V | Rising | 3 |
| Minimum VOUT for LOADTG to be On | | | 2.4 | 3 | V | VLOADEN = 5V | 3 |
| LOADTG On Voltage V(VOUT-LOADTG) | | 4.6 | 5 | 5.4 | V | VOUT = 12V | 3 |
| LOADTG Off Voltage V(VOUT-LOADTG) | | -0.1 | 0 | 0.1 | V | VOUT = 12V | 3 |
| Full Scale Current Regulation V(ISP-ISN) | | 97 | 100 | 103 | mV | VCTRL = 2V, VISP = 12V | 4 |
| ISMON Monitor Output VISMON | VISMON | 1.2 | 1.25 | 1.3 | V | V(ISP-ISN) = 100mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output VISMON | VISMON | 0.3 | 0.35 | 0.4 | V | V(ISP-ISN) = 10mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output VISMON | VISMON | 0.2 | 0.25 | 0.3 | V | V(ISP-ISN) = 0mV, VISP = 12V/0V | 4 |
| ISP/ISN Input Common Mode Range | | 0 | | 60 | V | | 4 |
| FB Regulation Voltage | | 0.985 | 1 | 1.015 | V | VC = 1.2V | 4 |
| Maximum Current Sense Threshold V(LSP-LSN), Buck | | 35 | 50 | 65 | mV | Buck, VFB = 0.8V | 4 |
| Maximum Current Sense Threshold V(LSP-LSN), Boost | | 40 | 50 | 60 | mV | Boost, VFB = 0.8V | 4 |
| FB Overvoltage Threshold (VFB) | VFB | 1.08 | 1.1 | 1.12 | V | Rising | 4 |
| FB Overvoltage Hysteresis | | 35 | 50 | 65 | mV | | 4 |
| FB Short Threshold (VFB) | VFB | 0.24 | 0.25 | 0.26 | V | Falling | 4 |
| FB Short Hysteresis | | 35 | 50 | 65 | mV | | 4 |
| PGOOD Upper Threshold Offset from VFB | | 8 | 10 | 12 | % | Rising | 4 |
| PGOOD Lower Threshold Offset from VFB | | -12 | -10 | -8 | % | Falling | 4 |
| SS Pull-Up Current | | 10.5 | 12.5 | 14.5 | µA | VFB = 0.4V, VSS = 0V | 4 |
| Switching Frequency | | 190 | 200 | 210 | kHz | VSYNC/SPRD = 0V, RT = 226kΩ | 5 |
| Switching Frequency | | 380 | 400 | 420 | kHz | VSYNC/SPRD = 0V, RT = 100kΩ | 5 |
| Switching Frequency | | 570 | 600 | 630 | kHz | VSYNC/SPRD = 0V, RT = 59.0kΩ | 5 |
| SYNC Frequency | | 150 | | 650 | kHz | | 5 |
| Highest Spread Spectrum Above Oscillator Frequency | | 12.5 | 14.5 | 16.5 | % | VSYNC/SPRD = 5V | 5 |
| Lowest Spread Spectrum Below Oscillator Frequency | | -17.7 | -15.7 | -13.7 | % | VSYNC/SPRD = 5V | 5 |
| Buck-Boost to Boost region transition | VIN/VOUT | 0.73 | 0.75 | 0.77 | | | 5 |
| Boost to Buck-Boost region transition | VIN/VOUT | 0.83 | 0.85 | 0.87 | | | 5 |
| Buck to Buck-Boost region transition | VIN/VOUT | 1.16 | 1.18 | 1.2 | | | 5 |
| Buck-Boost to Buck region transition | VIN/VOUT | 1.31 | 1.33 | 1.35 | | | 5 |
| Peak-Buck to Peak-Boost transition | VIN/VOUT | 0.96 | 0.98 | 1 | | | 5 |
| Peak-Boost to Peak-Buck transition | VIN/VOUT | 1 | 1.02 | 1.04 | | | 5 |
| TG1 Minimum Duty Cycle in Buck Region | | 10 | | | % | Peak-Buck Current Mode | 5 |
| TG1 Maximum Duty Cycle in Buck Region | | | | 95 | % | Peak-Buck Current Mode | 5 |
| BG2 Minimum Duty Cycle in Boost Region | | 10 | | | % | Peak-Boost Current Mode | 5 |
| BG2 Maximum Duty Cycle in Boost Region | | | | 95 | % | Peak-Boost Current Mode | 5 |
| Thermal resistance, junction-to-ambient (FE package) | θJA | | 30 | | °C/W | 28-lead plastic TSSOP (FE package) | 2 |
| Thermal resistance, junction-to-case (FE package) | θJC | | 5 | | °C/W | 28-lead plastic TSSOP (FE package) | 2 |
## CAD (KiCad official)
- Symbol: `LT8390EFE#TRPBF`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `lt8390efe-trpbf-etched.step` / `lt8390efe-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8390efe-trpbf.step` / `lt8390efe-trpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908025238704128) (32 pp, sha256 `b28ebec4c561175d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt8390efe-trpbf-datasheet.pdf)