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LT8333RDD#TRPBF

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ADI Others, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentotherslt8333rdd#trpbffactory-2.0.0extractor-text

Verified LT8333RDD#TRPBF

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 11 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT8333RDD#TRPBF · DFN-10(3x3) · 11 pins
  • ✓copper: 11 copper pads, none touching another net
  • ✓datasheet: all 11 pin names found in the 26-page datasheet
  • ✓distributor: lcsc C7460338, digikey 505-LT8333RDD#TRPBFTR-ND, mouser 584-LT8333RDD#TRPBF
  • ✓family: DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-myt_vqr2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 11 pins = 11 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 11 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt8333rdd-trpbf.kicad_sym✓ lt8333rdd-trpbf.kicad_mod✓ lt8333rdd-trpbf.step
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Ray Publish 0.1.0 2343c3a 3d ago

LT8333RDD#TRPBF

ADI · Others · DFN-10(3x3)

LT8333RDD#TRPBF from ADI, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN/UVLO input Shutdown and undervoltage lockout pin: the part stops switching below 1.6V, resumes above 1.68V, and draws less than 1µA from VIN when the pin is below 0.2V.
2 VIN power_in Input supply pin operating from 2.8V to 40V that must be locally bypassed with its input capacitor placed as close as possible to the pin.
3 INTVCC power_out Regulated 3.2V internal supply output that requires a minimum 1µF low ESR ceramic bypass to GND and no additional loading.
4 BIAS power_in Second input supply for INTVCC that is used when 4.4V ≤ BIAS ≤ VIN, and should be tied to GND if unused.
5 VC passive Error amplifier output pin to which the external compensation network is connected.
6 FBX input Voltage regulation feedback pin regulated to 1.60V for positive outputs or -0.80V for negative outputs, connected through a resistor divider from VOUT.
7 RT passive A resistor from this pin to the exposed pad GND programs the switching frequency over the 300kHz to 2MHz range.
8 SS passive Soft-start pin where a capacitor to GND controls the inductor current ramp rate during start-up, with 2µA charging current and a 220Ω pull-down during faults.
9 SYNC/MODE input Selects BURST, PULSE-SKIP, or SSFM operation, or synchronizes the switching frequency to an external clock, with a logic high threshold of 1.7V.
10 SW output Output of the internal 40V, 3A power switch, where the metal trace area should be minimized to reduce EMI.
11 GND power_in Power and signal ground exposed pad underneath the package that must be soldered to a continuous copper ground plane for heat removal.

Key specifications

Parameter Value
Manufacturer ADI
Package DFN-10(3x3)
Category Others
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SW pin voltage SW 40 V 2
VIN, EN/UVLO voltage VIN, EN/UVLO 40 V 2
BIAS voltage BIAS 40 V 2
SYNC voltage SYNC 6 V 2
VC voltage VC 4 V 2
FBX voltage FBX -4 4 V 2
Operating junction temperature range LT8333R TJ -40 150 °C LT8333R 2
Storage temperature range TSTG -65 150 °C 2
Maximum junction temperature TJ 150 °C 2
Thermal resistance junction to ambient θJA 43 °C/W 2
VIN operating voltage range VIN 2.8 40 V 2
VIN quiescent current at shutdown IQ 1 2 µA VEN/UVLO = 0.2V 2
VIN quiescent current at shutdown (full temperature range) IQ 1 15 µA VEN/UVLO = 0.2V, l 2
VIN quiescent current at shutdown IQ 2 5 µA VEN/UVLO = 1.5V 2
VIN quiescent current at shutdown (full temperature range) IQ 2 25 µA VEN/UVLO = 1.5V, l 2
VIN quiescent current sleep mode (not switching) IQ 9 15 µA SYNC = 0V 2
VIN quiescent current sleep mode (full temperature range) IQ 9 30 µA SYNC = 0V, l 2
VIN quiescent current active mode (not switching) IQ 1200 1600 µA SYNC = 0V or INTVCC, BIAS = 0V 2
VIN quiescent current active mode (full temperature range) IQ 1200 1850 µA SYNC = 0V or INTVCC, BIAS = 0V, l 2
VIN quiescent current active mode (not switching) IQ 22 40 µA SYNC = 0V or INTVCC, BIAS = 5V 2
VIN quiescent current active mode (full temperature range) IQ 22 65 µA SYNC = 0V or INTVCC, BIAS = 5V, l 2
BIAS threshold rising (BIAS can supply INTVCC) 4.4 4.65 V 2
BIAS threshold falling (BIAS cannot supply INTVCC) 4 4.25 V 2
FBX regulation voltage FBX 1.568 1.6 1.636 V FBX > 0V, l 2
FBX regulation voltage FBX -0.822 -0.8 -0.78 V FBX < 0V, l 2
FBX line regulation 0.005 0.015 %/V FBX > 0V, 2.8V < VIN < 40V 2
FBX pin current IFBX -10 10 nA FBX = 1.6V, -0.8V, l 2
Switching frequency fOSC fOSC 265 300 327 kHz RT = 165k, l 3
Switching frequency fOSC fOSC 0.9 1 1.08 MHz RT = 45.3k, l 3
Switching frequency fOSC fOSC 1.85 2 2.15 MHz RT = 20k, l 3
SSFM maximum frequency deviation ∆f/fOSC 14 20 25 % (∆f/fOSC) • 100, RT = 20k 3
Minimum on-time BURST mode 70 90 ns VIN = 12V (Note 6) 3
Minimum on-time PULSE SKIP mode 60 85 ns VIN = 12V (Note 6) 3
Minimum off-time 50 75 ns l 3
fSYNC/fOSC allowed ratio 0.95 1 1.25 kHz/kHz RT = 20k 3
SYNC pin current ISYNC 10 25 µA SYNC = 2V 3
SYNC pin current out of pin ISYNC 10 25 µA SYNC = 0V, current out of pin 3
Maximum switch current limit threshold ILIM 3 3.75 4.65 A l 3
Switch overcurrent threshold 5.6 A discharges SS pin 3
Switch RDS(ON) RDS(ON) 100 mΩ ISW = 0.5A 3
Switch leakage current ISW 0.1 1 µA VSW = 40V 3
EN/UVLO pin threshold rising 1.576 1.68 1.9 V start switching, l 3
EN/UVLO pin threshold falling 1.545 1.6 1.645 V stop switching, l 3
EN/UVLO pin current IEN/UVLO -75 75 nA VEN/UVLO = 1.6V, l 3
Soft-start charge current ISS 2 µA SS = 0.5V 3
Soft-start pull-down resistance RSS 220 Ω fault condition, SS = 0.1V 3
Error amplifier transconductance gm 75 µA/V FBX = 1.6V 3
Error amplifier transconductance gm 60 µA/V FBX = -0.8V 3
Error amplifier voltage gain 185 V/V FBX = 1.6V 3
Error amplifier voltage gain 145 V/V FBX = -0.8V 3
Error amplifier max source current 7 µA VC = 1.1V, current out of pin 3
Error amplifier max sink current 7 µA VC = 1.1V 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper the negative terminal as close as possible to the exposed pad PGND copper (near EN/UVLO). 6

CAD (KiCad official)

  • Symbol: LT8333RDD#TRPBF
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
  • 3D model files: lt8333rdd-trpbf-etched.step / lt8333rdd-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt8333rdd-trpbf.step / lt8333rdd-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ADI datasheet (26 pp, sha256 e67c94d5b86bb3b3, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF