component
LT8333RDD#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT8333RDD#PBF
Analog Devices · DC-DC Converters · DFN-10(3x3)
LT8333RDD#PBF from Analog Devices, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Shutdown and undervoltage detect pin: the part is off below 0.2V, stops switching below the 1.6V falling threshold, and resumes above 1.68V, with a 40V absolute maximum. |
| 2 | VIN | power_in | Input supply pin with a 2.8V to 40V operating range that must be locally bypassed with the input capacitor placed as close as possible to the pin. |
| 3 | INTVCC | power_out | Regulated 3.2V supply for internal loads that must be bypassed with a minimum 1µF low ESR ceramic capacitor to GND, and no additional components or loading are allowed on this pin. |
| 4 | BIAS | power_in | Second input supply for INTVCC that is used when 4.4V ≤ BIAS ≤ VIN to improve efficiency, with a 40V absolute maximum, and tied to GND if unused. |
| 5 | VC | passive | Error amplifier output pin to which the external compensation network is tied, with a 4V absolute maximum. |
| 6 | FBX | input | Voltage regulation feedback pin for positive or negative outputs, regulating to 1.6V in boost/SEPIC or -0.8V in inverting configurations, with a ±4V absolute maximum. |
| 7 | RT | passive | Resistor pin connected to the exposed pad GND that programs the switching frequency from 300kHz to 2MHz. |
| 8 | SS | passive | Soft-start pin where a capacitor to GND sets the inductor current ramp rate, charged at 2µA and discharged by an internal 220Ω MOSFET during shutdown or fault. |
| 9 | SYNC/MODE | input | Mode and clock input that selects BURST, PULSE-SKIP, SYNC or SSFM operation (GND or <0.14V for BURST, >1.7V or INTVCC for PULSE-SKIP/SSFM) and accepts an external clock, with a 6V absolute maximum. |
| 10 | SW | output | Output of the internal 3A, 40V power switch whose metal trace area should be minimized to reduce EMI. |
| 11 | PGND, GND | power_in | Power and signal ground connected to the exposed pad, which must be soldered to a continuous copper ground plane to conduct heat out of the package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Voltage Range | VIN | 2.8 | 40 | V | 2 | ||
| VIN Quiescent Current at Shutdown | 1 | 2 | μA | VEN/UVLO = 0.2V; TA = 25°C | 2 | ||
| VIN Quiescent Current at Shutdown | 1 | 15 | μA | VEN/UVLO = 0.2V; l (full operating temperature range) | 2 | ||
| VIN Quiescent Current at Shutdown | 2 | 5 | μA | VEN/UVLO = 1.5V; TA = 25°C | 2 | ||
| VIN Quiescent Current at Shutdown | 2 | 25 | μA | VEN/UVLO = 1.5V; l (full operating temperature range) | 2 | ||
| VIN Quiescent Current Sleep Mode (Not Switching) | 9 | 15 | μA | SYNC = 0V; TA = 25°C | 2 | ||
| VIN Quiescent Current Sleep Mode (Not Switching) | 9 | 30 | μA | SYNC = 0V; l (full operating temperature range) | 2 | ||
| VIN Quiescent Current Active Mode (Not Switching) | 1200 | 1600 | μA | SYNC = 0V or INTVCC, BIAS = 0V; TA = 25°C | 2 | ||
| VIN Quiescent Current Active Mode (Not Switching) | 1200 | 1850 | μA | SYNC = 0V or INTVCC, BIAS = 0V; l (full operating temperature range) | 2 | ||
| VIN Quiescent Current Active Mode (Not Switching) | 22 | 40 | μA | SYNC = 0V or INTVCC, BIAS = 5V; TA = 25°C | 2 | ||
| VIN Quiescent Current Active Mode (Not Switching) | 22 | 65 | μA | SYNC = 0V or INTVCC, BIAS = 5V; l (full operating temperature range) | 2 | ||
| BIAS Threshold Rising (BIAS can supply INTVCC) | 4.4 | 4.65 | V | Rising | 2 | ||
| BIAS Threshold Falling (BIAS cannot supply INTVCC) | 4 | 4.25 | V | Falling | 2 | ||
| FBX Regulation Voltage (FBX > 0V) | 1.568 | 1.6 | 1.636 | V | FBX > 0V; l (full operating temperature range) | 2 | |
| FBX Regulation Voltage (FBX < 0V) | -0.822 | -0.8 | -0.78 | V | FBX < 0V; l (full operating temperature range) | 2 | |
| FBX Line Regulation (FBX > 0V) | 0.005 | 0.015 | %/V | FBX > 0V, 2.8V < VIN < 40V | 2 | ||
| FBX Line Regulation (FBX < 0V) | 0.005 | 0.015 | %/V | FBX < 0V, 2.8V < VIN < 40V | 2 | ||
| FBX Pin Current | -10 | 10 | nA | FBX = 1.6V, -0.8V; l (full operating temperature range) | 2 | ||
| Switching Frequency (RT = 165k) | fOSC | 265 | 300 | 327 | kHz | RT = 165k; l (full operating temperature range) | 3 |
| Switching Frequency (RT = 45.3k) | fOSC | 0.9 | 1 | 1.08 | MHz | RT = 45.3k; l (full operating temperature range) | 3 |
| Switching Frequency (RT = 20k) | fOSC | 1.85 | 2 | 2.15 | MHz | RT = 20k; l (full operating temperature range) | 3 |
| SSFM Maximum Frequency Deviation | ∆f/fOSC | 14 | 20 | 25 | % | (∆f/fOSC) • 100, RT = 20k | 3 |
| Minimum On-Time (BURST Mode) | 70 | 90 | ns | BURST Mode, VIN = 12V (Note 6) | 3 | ||
| Minimum On-Time (PULSE SKIP Mode) | 60 | 85 | ns | PULSE SKIP Mode, VIN = 12V (Note 6) | 3 | ||
| Minimum Off-Time | 50 | 75 | ns | l (full operating temperature range) | 3 | ||
| SYNC/MODE Mode Threshold High (Rising) | 1.3 | 1.7 | V | l (full operating temperature range) | 3 | ||
| SYNC/MODE Mode Threshold Low (Falling) | 0.14 | 0.2 | V | l (full operating temperature range) | 3 | ||
| SYNC/MODE Clock Threshold Rising | 1.3 | 1.7 | V | l (full operating temperature range) | 3 | ||
| SYNC/MODE Clock Threshold Falling | 0.4 | 0.8 | V | l (full operating temperature range) | 3 | ||
| fSYNC/fOSC Allowed Ratio | 0.95 | 1 | 1.25 | kHz/kHz | RT = 20k | 3 | |
| SYNC Pin Current | 10 | 25 | μA | SYNC = 2V | 3 | ||
| Maximum Switch Current Limit Threshold | 3 | 3.75 | 4.65 | A | l (full operating temperature range) | 3 | |
| Switch Leakage Current | 0.1 | 1 | μA | VSW = 40V | 3 | ||
| EN/UVLO Pin Threshold (Rising, start switching) | 1.576 | 1.68 | 1.9 | V | Start switching; l (full operating temperature range) | 3 | |
| EN/UVLO Pin Threshold (Falling, stop switching) | 1.545 | 1.6 | 1.645 | V | Stop switching; l (full operating temperature range) | 3 | |
| EN/UVLO Pin Current | -75 | 75 | nA | VEN/UVLO = 1.6V; l (full operating temperature range) | 3 | ||
| SW pin voltage (absolute maximum) | 40 | V | 2 | ||||
| VIN, EN/UVLO pin voltage (absolute maximum) | 40 | V | 2 | ||||
| BIAS pin voltage (absolute maximum) | 40 | V | 2 | ||||
| SYNC pin voltage (absolute maximum) | 6 | V | 2 | ||||
| VC pin voltage (absolute maximum) | 4 | V | 2 | ||||
| FBX pin voltage (absolute maximum) | -4 | 4 | V | 2 | |||
| Operating Junction Temperature Range (LT8333R) | -40 | 150 | °C | LT8333R | 2 | ||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Maximum Junction Temperature | 150 | °C | 2 | ||||
| Switch Overcurrent Threshold (discharges SS pin) | 5.6 | A | 3 | ||||
| Switch RDS(ON) | 100 | mΩ | ISW = 0.5A | 3 | |||
| Soft-Start Charge Current | 2 | µA | SS = 0.5V | 3 | |||
| Soft-Start Pull-Down Resistance | 220 | Ω | Fault Condition, SS = 0.1V | 3 | |||
| Error Amplifier Transconductance | 75 | µA/V | FBX = 1.6V | 3 | |||
| Error Amplifier Transconductance | 60 | µA/V | FBX = -0.8V | 3 | |||
| Error Amplifier Voltage Gain | 185 | V/V | FBX = 1.6V | 3 | |||
| Error Amplifier Voltage Gain | 145 | V/V | FBX = -0.8V | 3 | |||
| Error Amplifier Max Source Current | 7 | µA | VC = 1.1V, current out of pin | 3 | |||
| Error Amplifier Max Sink Current | 7 | µA | VC = 1.1V | 3 | |||
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | 43 | °C/W | DD package, 10-lead (3mm × 3mm) plastic DFN | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | the negative terminal as close as possible to the exposed pad PGND copper (near EN/UVLO). | 6 |
CAD (KiCad official)
- Symbol:
LT8333RDD#PBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
lt8333rdd-pbf-etched.step/lt8333rdd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8333rdd-pbf.step/lt8333rdd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
e67c94d5b86bb3b3, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT8333RDD#PBF
**Analog Devices** · DC-DC Converters · DFN-10(3x3)
LT8333RDD#PBF from Analog Devices, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Shutdown and undervoltage detect pin: the part is off below 0.2V, stops switching below the 1.6V falling threshold, and resumes above 1.68V, with a 40V absolute maximum. |
| 2 | VIN | power_in | Input supply pin with a 2.8V to 40V operating range that must be locally bypassed with the input capacitor placed as close as possible to the pin. |
| 3 | INTVCC | power_out | Regulated 3.2V supply for internal loads that must be bypassed with a minimum 1µF low ESR ceramic capacitor to GND, and no additional components or loading are allowed on this pin. |
| 4 | BIAS | power_in | Second input supply for INTVCC that is used when 4.4V ≤ BIAS ≤ VIN to improve efficiency, with a 40V absolute maximum, and tied to GND if unused. |
| 5 | VC | passive | Error amplifier output pin to which the external compensation network is tied, with a 4V absolute maximum. |
| 6 | FBX | input | Voltage regulation feedback pin for positive or negative outputs, regulating to 1.6V in boost/SEPIC or -0.8V in inverting configurations, with a ±4V absolute maximum. |
| 7 | RT | passive | Resistor pin connected to the exposed pad GND that programs the switching frequency from 300kHz to 2MHz. |
| 8 | SS | passive | Soft-start pin where a capacitor to GND sets the inductor current ramp rate, charged at 2µA and discharged by an internal 220Ω MOSFET during shutdown or fault. |
| 9 | SYNC/MODE | input | Mode and clock input that selects BURST, PULSE-SKIP, SYNC or SSFM operation (GND or <0.14V for BURST, >1.7V or INTVCC for PULSE-SKIP/SSFM) and accepts an external clock, with a 6V absolute maximum. |
| 10 | SW | output | Output of the internal 3A, 40V power switch whose metal trace area should be minimized to reduce EMI. |
| 11 | PGND, GND | power_in | Power and signal ground connected to the exposed pad, which must be soldered to a continuous copper ground plane to conduct heat out of the package. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Voltage Range | VIN | 2.8 | | 40 | V | | 2 |
| VIN Quiescent Current at Shutdown | | | 1 | 2 | μA | VEN/UVLO = 0.2V; TA = 25°C | 2 |
| VIN Quiescent Current at Shutdown | | | 1 | 15 | μA | VEN/UVLO = 0.2V; l (full operating temperature range) | 2 |
| VIN Quiescent Current at Shutdown | | | 2 | 5 | μA | VEN/UVLO = 1.5V; TA = 25°C | 2 |
| VIN Quiescent Current at Shutdown | | | 2 | 25 | μA | VEN/UVLO = 1.5V; l (full operating temperature range) | 2 |
| VIN Quiescent Current Sleep Mode (Not Switching) | | | 9 | 15 | μA | SYNC = 0V; TA = 25°C | 2 |
| VIN Quiescent Current Sleep Mode (Not Switching) | | | 9 | 30 | μA | SYNC = 0V; l (full operating temperature range) | 2 |
| VIN Quiescent Current Active Mode (Not Switching) | | | 1200 | 1600 | μA | SYNC = 0V or INTVCC, BIAS = 0V; TA = 25°C | 2 |
| VIN Quiescent Current Active Mode (Not Switching) | | | 1200 | 1850 | μA | SYNC = 0V or INTVCC, BIAS = 0V; l (full operating temperature range) | 2 |
| VIN Quiescent Current Active Mode (Not Switching) | | | 22 | 40 | μA | SYNC = 0V or INTVCC, BIAS = 5V; TA = 25°C | 2 |
| VIN Quiescent Current Active Mode (Not Switching) | | | 22 | 65 | μA | SYNC = 0V or INTVCC, BIAS = 5V; l (full operating temperature range) | 2 |
| BIAS Threshold Rising (BIAS can supply INTVCC) | | 4.4 | | 4.65 | V | Rising | 2 |
| BIAS Threshold Falling (BIAS cannot supply INTVCC) | | 4 | | 4.25 | V | Falling | 2 |
| FBX Regulation Voltage (FBX > 0V) | | 1.568 | 1.6 | 1.636 | V | FBX > 0V; l (full operating temperature range) | 2 |
| FBX Regulation Voltage (FBX < 0V) | | -0.822 | -0.8 | -0.78 | V | FBX < 0V; l (full operating temperature range) | 2 |
| FBX Line Regulation (FBX > 0V) | | | 0.005 | 0.015 | %/V | FBX > 0V, 2.8V < VIN < 40V | 2 |
| FBX Line Regulation (FBX < 0V) | | | 0.005 | 0.015 | %/V | FBX < 0V, 2.8V < VIN < 40V | 2 |
| FBX Pin Current | | -10 | | 10 | nA | FBX = 1.6V, -0.8V; l (full operating temperature range) | 2 |
| Switching Frequency (RT = 165k) | fOSC | 265 | 300 | 327 | kHz | RT = 165k; l (full operating temperature range) | 3 |
| Switching Frequency (RT = 45.3k) | fOSC | 0.9 | 1 | 1.08 | MHz | RT = 45.3k; l (full operating temperature range) | 3 |
| Switching Frequency (RT = 20k) | fOSC | 1.85 | 2 | 2.15 | MHz | RT = 20k; l (full operating temperature range) | 3 |
| SSFM Maximum Frequency Deviation | ∆f/fOSC | 14 | 20 | 25 | % | (∆f/fOSC) • 100, RT = 20k | 3 |
| Minimum On-Time (BURST Mode) | | | 70 | 90 | ns | BURST Mode, VIN = 12V (Note 6) | 3 |
| Minimum On-Time (PULSE SKIP Mode) | | | 60 | 85 | ns | PULSE SKIP Mode, VIN = 12V (Note 6) | 3 |
| Minimum Off-Time | | 50 | | 75 | ns | l (full operating temperature range) | 3 |
| SYNC/MODE Mode Threshold High (Rising) | | 1.3 | | 1.7 | V | l (full operating temperature range) | 3 |
| SYNC/MODE Mode Threshold Low (Falling) | | 0.14 | | 0.2 | V | l (full operating temperature range) | 3 |
| SYNC/MODE Clock Threshold Rising | | 1.3 | | 1.7 | V | l (full operating temperature range) | 3 |
| SYNC/MODE Clock Threshold Falling | | 0.4 | | 0.8 | V | l (full operating temperature range) | 3 |
| fSYNC/fOSC Allowed Ratio | | 0.95 | 1 | 1.25 | kHz/kHz | RT = 20k | 3 |
| SYNC Pin Current | | | 10 | 25 | μA | SYNC = 2V | 3 |
| Maximum Switch Current Limit Threshold | | 3 | 3.75 | 4.65 | A | l (full operating temperature range) | 3 |
| Switch Leakage Current | | | 0.1 | 1 | μA | VSW = 40V | 3 |
| EN/UVLO Pin Threshold (Rising, start switching) | | 1.576 | 1.68 | 1.9 | V | Start switching; l (full operating temperature range) | 3 |
| EN/UVLO Pin Threshold (Falling, stop switching) | | 1.545 | 1.6 | 1.645 | V | Stop switching; l (full operating temperature range) | 3 |
| EN/UVLO Pin Current | | -75 | | 75 | nA | VEN/UVLO = 1.6V; l (full operating temperature range) | 3 |
| SW pin voltage (absolute maximum) | | | | 40 | V | | 2 |
| VIN, EN/UVLO pin voltage (absolute maximum) | | | | 40 | V | | 2 |
| BIAS pin voltage (absolute maximum) | | | | 40 | V | | 2 |
| SYNC pin voltage (absolute maximum) | | | | 6 | V | | 2 |
| VC pin voltage (absolute maximum) | | | | 4 | V | | 2 |
| FBX pin voltage (absolute maximum) | | -4 | | 4 | V | | 2 |
| Operating Junction Temperature Range (LT8333R) | | -40 | | 150 | °C | LT8333R | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Maximum Junction Temperature | | | | 150 | °C | | 2 |
| Switch Overcurrent Threshold (discharges SS pin) | | | 5.6 | | A | | 3 |
| Switch RDS(ON) | | | 100 | | mΩ | ISW = 0.5A | 3 |
| Soft-Start Charge Current | | | 2 | | µA | SS = 0.5V | 3 |
| Soft-Start Pull-Down Resistance | | | 220 | | Ω | Fault Condition, SS = 0.1V | 3 |
| Error Amplifier Transconductance | | | 75 | | µA/V | FBX = 1.6V | 3 |
| Error Amplifier Transconductance | | | 60 | | µA/V | FBX = -0.8V | 3 |
| Error Amplifier Voltage Gain | | | 185 | | V/V | FBX = 1.6V | 3 |
| Error Amplifier Voltage Gain | | | 145 | | V/V | FBX = -0.8V | 3 |
| Error Amplifier Max Source Current | | | 7 | | µA | VC = 1.1V, current out of pin | 3 |
| Error Amplifier Max Sink Current | | | 7 | | µA | VC = 1.1V | 3 |
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | | 43 | | °C/W | DD package, 10-lead (3mm × 3mm) plastic DFN | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | the negative terminal as close as possible to the exposed pad PGND copper (near EN/UVLO). | 6 |
## CAD (KiCad official)
- Symbol: `LT8333RDD#PBF`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files: `lt8333rdd-pbf-etched.step` / `lt8333rdd-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt8333rdd-pbf.step` / `lt8333rdd-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903634689540096) (26 pp, sha256 `e67c94d5b86bb3b3`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt8333rdd-pbf-datasheet.pdf)