component
LT6370AIS8E#PBF
Public Made by Adomby adom
Analog Devices Instrumentation OpAmps, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT6370AIS8E#PBF
Analog Devices · Instrumentation OpAmps · SOIC-8-EP
LT6370AIS8E#PBF from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | -RG | passive | Connection for the external gain setting resistor between -RG and +RG, with gain G = 1 + 24.2k/RG. |
| 2 | -IN | input | Negative input terminal, high impedance, with integrated EMI filter and input voltage range of (V- - 0.3V) to (V+ + 0.3V). |
| 3 | +IN | input | Positive input terminal, high impedance, with integrated EMI filter and input voltage range of (V- - 0.3V) to (V+ + 0.3V). |
| 4 | V- | power_in | Negative power supply, to be bypassed with a capacitor between supply pins and ground; total supply (V+ to V-) is 36V max. |
| 5 | REF | input | Reference input for the output voltage, with input range of (V- - 0.3V) to (V+ + 0.3V). |
| 6 | OUTPUT | output | Output voltage referenced to the REF pin, with output current up to 80mA and thermally limited short-circuit duration. |
| 7 | V+ | power_in | Positive power supply, to be bypassed with a capacitor between supply pins and ground; total supply (V+ to V-) is 36V max. |
| 8 | +RG | passive | Connection for the external gain setting resistor between -RG and +RG, with gain G = 1 + 24.2k/RG. |
| 9 | EP | passive | Exposed pad must float or be connected to V+ in addition to pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Amplifiers |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Total supply voltage (V+ to V-) | 36 | V | 2 | ||||
| Differential input voltage | -36 | 36 | V | +IN to -IN | 2 | ||
| Input current (+RG, -RG) | -2 | 2 | mA | 2 | |||
| Input current (+IN, -IN) | -10 | 10 | mA | 2 | |||
| Maximum junction temperature | 150 | °C | 2 | ||||
| Storage temperature range | -65 | 150 | °C | 2 | |||
| Lead temperature | 300 | °C | Soldering, 10 sec | 2 | |||
| Operating and specified temperature range, I-grade | -40 | 85 | °C | I-Grade | 2 | ||
| Supply voltage | VS | 4.75 | 35 | V | Guaranteed by PSRR | 5 | |
| Thermal resistance junction-to-ambient, S8E | θJA | 33 | °C/W | S8E package | 2 | ||
| Thermal resistance junction-to-case, S8E | θJC | 5 | °C/W | S8E package | 2 | ||
| Gain error, G = 1 | -0.004 | 0.01 | % | G = 1 | 3 | ||
| Gain error, G = 10 | -0.02 | 0.08 | % | G = 10 | 3 | ||
| Gain error, G = 10, 85°C | 0.4 | % | G = 10, TA = -40°C to 85°C | 3 | |||
| Gain error, G = 100 | -0.02 | 0.08 | % | G = 100 | 3 | ||
| Gain error, G = 100, 85°C | 0.4 | % | G = 100, TA = -40°C to 85°C | 3 | |||
| Gain error, G = 1000 | -0.05 | 0.15 | % | G = 1000 | 3 | ||
| Gain error, G = 1000, 85°C | 0.47 | % | G = 1000, TA = -40°C to 85°C | 3 | |||
| Gain vs temperature, G = 1 | 0.2 | 0.5 | ppm/°C | G = 1 | 3 | ||
| Gain vs temperature, G > 1 | 20 | 30 | ppm/°C | G > 1 | 3 | ||
| Gain nonlinearity, G = 1 | 1 | 3 | ppm | VOUT = ±10V, G = 1 | 3 | ||
| Gain nonlinearity, G = 10 | 3 | 20 | ppm | VOUT = ±10V, G = 10 | 3 | ||
| Gain nonlinearity, G = 100 | 20 | 30 | ppm | VOUT = ±10V, G = 100 | 3 | ||
| Gain nonlinearity, G = 1000 | 50 | 200 | ppm | VOUT = ±10V, G = 1000 | 3 | ||
| Input offset voltage, S8E | VOSI | -25 | 9 | 25 | μV | S8E Package | 3 |
| Output offset voltage, S8E | VOSO | -165 | 60 | 165 | μV | S8E Package | 3 |
| Input offset voltage drift, S8E, 85°C | ΔVOSI/ΔT | -0.3 | 0.3 | μV/°C | S8E Package, TA = -40°C to 85°C | 3 | |
| Input offset voltage hysteresis, 85°C | 1.5 | μV | TA = -40°C to 85°C | 3 | |||
| Input bias current, MS8 and S8E | IB | -0.4 | 0.1 | 0.4 | nA | MS8 and S8E Packages | 4 |
| Input offset current, MS8 and S8E | IOS | -0.7 | 0.2 | 0.7 | nA | MS8 and S8E Packages | 4 |
| CMRR, G = 1 | CMRR | 94 | 112 | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1 | 4 | |
| CMRR, G = 1, over temperature | CMRR | 87 | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1, over temperature range | 4 | ||
| CMRR, G = 10 | CMRR | 112 | 132 | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 10 | 4 | |
| CMRR, G = 100 | CMRR | 126 | 144 | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 100 | 4 | |
| CMRR, G = 1000 | CMRR | 134 | 148 | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1000 | 4 | |
| PSRR, G = 1 | PSRR | 116 | 130 | dB | VS = ±2.375V to ±17.5V, G = 1 | 5 | |
| PSRR, G = 10 | PSRR | 134 | 140 | dB | VS = ±2.375V to ±17.5V, G = 10 | 5 | |
| PSRR, G = 100 | PSRR | 136 | 142 | dB | VS = ±2.375V to ±17.5V, G = 100 | 5 | |
| PSRR, G = 1000 | PSRR | 136 | 146 | dB | VS = ±2.375V to ±17.5V, G = 1000 | 5 | |
| Supply current, ±15V | IS | 2.65 | 2.75 | mA | VS = ±15V | 5 | |
| Supply current, ±15V, 85°C | IS | 2.9 | mA | VS = ±15V, TA = -40°C to 85°C | 5 | ||
| Supply current, ±2.375V | IS | 2.55 | 2.6 | mA | VS = ±2.375V | 5 | |
| Supply current, ±2.375V, 85°C | IS | 2.75 | mA | VS = ±2.375V, TA = -40°C to 85°C | 5 | ||
| Output short circuit current | IOUT | 35 | 55 | mA | 5 | ||
| Slew rate | SR | 8 | 11 | V/μs | G = 1, VOUT = ±10V | 5 | |
| REF gain error | -80 | -20 | 40 | ppm | VREF = ±10V | 5 | |
| -3dB bandwidth, G = 1 | BW | 3100 | kHz | G = 1 | 5 | ||
| REF input resistance | RREFIN | 20 | kΩ | 5 | |||
| Input noise voltage density | eni | 7 | nV/√Hz | f = 1kHz | 4 | ||
| Input resistance | RIN | 225 | GΩ | VIN = -12.6V to 13V | 4 |
CAD (KiCad official)
- Symbol:
LT6370AIS8E#PBF - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
lt6370ais8e-pbf-etched.step/lt6370ais8e-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt6370ais8e-pbf.step/lt6370ais8e-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
2178fbfb81bf59fe, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT6370AIS8E#PBF
**Analog Devices** · Instrumentation OpAmps · SOIC-8-EP
LT6370AIS8E#PBF from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | -RG | passive | Connection for the external gain setting resistor between -RG and +RG, with gain G = 1 + 24.2k/RG. |
| 2 | -IN | input | Negative input terminal, high impedance, with integrated EMI filter and input voltage range of (V- - 0.3V) to (V+ + 0.3V). |
| 3 | +IN | input | Positive input terminal, high impedance, with integrated EMI filter and input voltage range of (V- - 0.3V) to (V+ + 0.3V). |
| 4 | V- | power_in | Negative power supply, to be bypassed with a capacitor between supply pins and ground; total supply (V+ to V-) is 36V max. |
| 5 | REF | input | Reference input for the output voltage, with input range of (V- - 0.3V) to (V+ + 0.3V). |
| 6 | OUTPUT | output | Output voltage referenced to the REF pin, with output current up to 80mA and thermally limited short-circuit duration. |
| 7 | V+ | power_in | Positive power supply, to be bypassed with a capacitor between supply pins and ground; total supply (V+ to V-) is 36V max. |
| 8 | +RG | passive | Connection for the external gain setting resistor between -RG and +RG, with gain G = 1 + 24.2k/RG. |
| 9 | EP | passive | Exposed pad must float or be connected to V+ in addition to pin 7. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8-EP |
| Category | Amplifiers |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Total supply voltage (V+ to V-) | | | | 36 | V | | 2 |
| Differential input voltage | | -36 | | 36 | V | +IN to -IN | 2 |
| Input current (+RG, -RG) | | -2 | | 2 | mA | | 2 |
| Input current (+IN, -IN) | | -10 | | 10 | mA | | 2 |
| Maximum junction temperature | | | | 150 | °C | | 2 |
| Storage temperature range | | -65 | | 150 | °C | | 2 |
| Lead temperature | | | | 300 | °C | Soldering, 10 sec | 2 |
| Operating and specified temperature range, I-grade | | -40 | | 85 | °C | I-Grade | 2 |
| Supply voltage | VS | 4.75 | | 35 | V | Guaranteed by PSRR | 5 |
| Thermal resistance junction-to-ambient, S8E | θJA | | 33 | | °C/W | S8E package | 2 |
| Thermal resistance junction-to-case, S8E | θJC | | 5 | | °C/W | S8E package | 2 |
| Gain error, G = 1 | | | -0.004 | 0.01 | % | G = 1 | 3 |
| Gain error, G = 10 | | | -0.02 | 0.08 | % | G = 10 | 3 |
| Gain error, G = 10, 85°C | | | | 0.4 | % | G = 10, TA = -40°C to 85°C | 3 |
| Gain error, G = 100 | | | -0.02 | 0.08 | % | G = 100 | 3 |
| Gain error, G = 100, 85°C | | | | 0.4 | % | G = 100, TA = -40°C to 85°C | 3 |
| Gain error, G = 1000 | | | -0.05 | 0.15 | % | G = 1000 | 3 |
| Gain error, G = 1000, 85°C | | | | 0.47 | % | G = 1000, TA = -40°C to 85°C | 3 |
| Gain vs temperature, G = 1 | | | 0.2 | 0.5 | ppm/°C | G = 1 | 3 |
| Gain vs temperature, G > 1 | | | 20 | 30 | ppm/°C | G > 1 | 3 |
| Gain nonlinearity, G = 1 | | | 1 | 3 | ppm | VOUT = ±10V, G = 1 | 3 |
| Gain nonlinearity, G = 10 | | | 3 | 20 | ppm | VOUT = ±10V, G = 10 | 3 |
| Gain nonlinearity, G = 100 | | | 20 | 30 | ppm | VOUT = ±10V, G = 100 | 3 |
| Gain nonlinearity, G = 1000 | | | 50 | 200 | ppm | VOUT = ±10V, G = 1000 | 3 |
| Input offset voltage, S8E | VOSI | -25 | 9 | 25 | μV | S8E Package | 3 |
| Output offset voltage, S8E | VOSO | -165 | 60 | 165 | μV | S8E Package | 3 |
| Input offset voltage drift, S8E, 85°C | ΔVOSI/ΔT | -0.3 | | 0.3 | μV/°C | S8E Package, TA = -40°C to 85°C | 3 |
| Input offset voltage hysteresis, 85°C | | | 1.5 | | μV | TA = -40°C to 85°C | 3 |
| Input bias current, MS8 and S8E | IB | -0.4 | 0.1 | 0.4 | nA | MS8 and S8E Packages | 4 |
| Input offset current, MS8 and S8E | IOS | -0.7 | 0.2 | 0.7 | nA | MS8 and S8E Packages | 4 |
| CMRR, G = 1 | CMRR | 94 | 112 | | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1 | 4 |
| CMRR, G = 1, over temperature | CMRR | 87 | | | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1, over temperature range | 4 |
| CMRR, G = 10 | CMRR | 112 | 132 | | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 10 | 4 |
| CMRR, G = 100 | CMRR | 126 | 144 | | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 100 | 4 |
| CMRR, G = 1000 | CMRR | 134 | 148 | | dB | DC to 60Hz, 1k Source Imbalance, VCM = -12.6V to 13V, G = 1000 | 4 |
| PSRR, G = 1 | PSRR | 116 | 130 | | dB | VS = ±2.375V to ±17.5V, G = 1 | 5 |
| PSRR, G = 10 | PSRR | 134 | 140 | | dB | VS = ±2.375V to ±17.5V, G = 10 | 5 |
| PSRR, G = 100 | PSRR | 136 | 142 | | dB | VS = ±2.375V to ±17.5V, G = 100 | 5 |
| PSRR, G = 1000 | PSRR | 136 | 146 | | dB | VS = ±2.375V to ±17.5V, G = 1000 | 5 |
| Supply current, ±15V | IS | | 2.65 | 2.75 | mA | VS = ±15V | 5 |
| Supply current, ±15V, 85°C | IS | | | 2.9 | mA | VS = ±15V, TA = -40°C to 85°C | 5 |
| Supply current, ±2.375V | IS | | 2.55 | 2.6 | mA | VS = ±2.375V | 5 |
| Supply current, ±2.375V, 85°C | IS | | | 2.75 | mA | VS = ±2.375V, TA = -40°C to 85°C | 5 |
| Output short circuit current | IOUT | 35 | 55 | | mA | | 5 |
| Slew rate | SR | 8 | 11 | | V/μs | G = 1, VOUT = ±10V | 5 |
| REF gain error | | -80 | -20 | 40 | ppm | VREF = ±10V | 5 |
| -3dB bandwidth, G = 1 | BW | | 3100 | | kHz | G = 1 | 5 |
| REF input resistance | RREFIN | | 20 | | kΩ | | 5 |
| Input noise voltage density | eni | | 7 | | nV/√Hz | f = 1kHz | 4 |
| Input resistance | RIN | | 225 | | GΩ | VIN = -12.6V to 13V | 4 |
## CAD (KiCad official)
- Symbol: `LT6370AIS8E#PBF`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `lt6370ais8e-pbf-etched.step` / `lt6370ais8e-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt6370ais8e-pbf.step` / `lt6370ais8e-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/LT6370.pdf) (28 pp, sha256 `2178fbfb81bf59fe`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt6370ais8e-pbf-datasheet.pdf)