# LT4275AIDD#TRPBF

**Analog Devices** · Ethernet ICs · DFN-10-EP(3x3)

LT4275AIDD#TRPBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IEEEUVLO | input | Hot Swap turn-on threshold level control; connect to ground for IEEE compliant turn-on/turn-off UVLO thresholds, leave open for lower thresholds. |
| 2 | AUX | input | Auxiliary sense input set via resistive divider (threshold VAUXT 6.3V typ); asserting it pulls down HSGATE, disconnects the signature resistor, disables classification and floats PWRGD, sinks IAUXH below threshold for hysteresis, tie to GND when not used. |
| 3 | RCLASS | passive | Programmable PoE classification resistor pin, resistor to GND per Table 1 (float for class 0). |
| 4 | RCLASS++ | passive | Programmable LTPoE++ classification resistor pin, used on the LT4275A (not connected on LT4275B/C), value per Table 1. |
| 5 | GND | power_in | Ground pin, must be soldered to PCB GND. |
| 6 | T2P | output | PSE type indicator open-drain output (LT4275A/B only); floats for 13W PSE, pulls down for 25.5W PSE, and toggles at fT2P (690-990Hz, ~50% duty) for an LTPoE++ PSE, valid after PWRGD is active; absolute maximum 100V, 5mA. |
| 7 | PWRGD | output | Power good open-drain output that pulls down during VCLASS and inrush; absolute maximum 100V, 5mA, output low 0.8V max at 1mA. |
| 8 | HSSRC | passive | External Hot Swap MOSFET source connection; absolute maximum -0.3V to 100V. |
| 9 | HSGATE | output | External Hot Swap MOSFET gate control output, connect to MOSFET gate; absolute maximum current ±20mA. |
| 10 | VPORT | power_in | PD interface upper power rail and external Hot Swap MOSFET drain connection; operating 23V to 60V, absolute maximum 100V. |
| 11 | GND | power_in | Exposed pad, internally connected to GND, must be soldered to PCB GND and only connected to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Interface ICs |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Input Voltage | VPORT |  |  | 60 | V | At VPORT Pin | 3 |
| VPORT Signature Range | VSIG | 1.5 |  | 10 | V | At VPORT Pin | 3 |
| VPORT Classification Range | VCLASS | 12.5 |  | 21 | V | At VPORT Pin | 3 |
| VPORT Mark Range | VMARK | 5.6 |  | 10 | V | At VPORT Pin, Preceded by VCLASS | 3 |
| VPORT Aux Mode Range |  | 8 |  | 60 | V | At VPORT Pin, AUX > VAUXT | 3 |
| Reset Threshold | VRESET | 2.6 |  | 5.6 | V |  | 3 |
| Hot Swap Turn-On Voltage | VHSON | 35 |  | 37 | V | IEEEUVLO = 0V | 3 |
| Hot Swap Turn-On Voltage | VHSON | 27 |  | 29 | V | IEEEUVLO Open | 3 |
| Hot Swap Turn-Off Voltage | VHSOFF | 30 |  | 31 | V | IEEEUVLO = 0V | 3 |
| Hot Swap Turn-Off Voltage | VHSOFF | 21.5 |  | 22.5 | V | IEEEUVLO Open | 3 |
| Supply Current |  |  |  | 2 | mA | VPORT = HSSRC = 57V | 3 |
| Supply Current During Classification |  | 0.4 | 0.7 | 1.1 | mA | VPORT = 17.5V, RCLASS and RCLASS++ Open | 3 |
| Supply Current During Mark Event |  | 0.5 |  | 2.2 | mA | VMARK | 3 |
| Signature Resistance |  | 23.7 | 24.4 | 25.2 | kΩ | VSIG (Note 2) | 3 |
| Signature Resistance During Mark Event |  | 5.8 | 8.3 | 11 | kΩ | VMARK (Note 2) | 3 |
| RCLASS/RCLASS++ Operating Voltage | VRCLS | 1.32 | 1.4 | 1.43 | V | -10mA ≥ IRCLASS ≥ -36mA, VCLASS | 3 |
| Classification Stability Time |  |  |  | 2 | ms | VPORT Step to 17.5V, RCLASS = 34.8Ω | 3 |
| AUX Threshold | VAUXT | 6.1 | 6.3 | 6.5 | V |  | 3 |
| AUX Pin Hysteresis Current | IAUXH | 4 | 5.8 | 8 | µA | AUX = 6.1V | 3 |
| T2P Output Low |  |  |  | 0.8 | V | 1mA Load | 3 |
| PWRGD Output Low |  |  |  | 0.8 | V | 1mA Load | 3 |
| PWRGD Leakage Current |  |  |  | 5 | µA | PWRGD = 60V | 3 |
| T2P Leakage Current |  |  |  | 5 | µA | T2P = 60V | 3 |
| HSGATE Pull-Up Current | IGPU | 18 | 22 | 27 | µA | VHSGATE, VHSSRC = 5V, VPORT > 42V, Out of Pin | 3 |
| HSGATE Open Circuit Voltage | VGOC | 10 |  | 18 | V | VHSGATE, VHSSRC, 0µA to 10µA Load with Respect to HSSRC | 3 |
| T2P Frequency | fT2P | 690 | 840 | 990 | Hz | After PWRGD Valid, if LTPoE++ PSE Is Mutually Identified | 3 |
| VPORT, HSSRC Voltage |  | -0.3 |  | 100 | V |  | 2 |
| HSGATE Current |  | -20 |  | 20 | mA |  | 2 |
| IEEEUVLO, RCLASS, RCLASS++ Voltage |  | -0.3 |  | 8 | V | and ≤ VPORT | 2 |
| AUX Current |  | -1.4 |  | 1.4 | mA |  | 2 |
| T2P, PWRGD Voltage |  | -0.3 |  | 100 | V |  | 2 |
| T2P, PWRGD Current |  |  |  | 5 | mA |  | 2 |
| Operating Junction Temperature Range (LT4275AI) |  | -40 |  | 85 | °C |  | 2 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 2 |
| Maximum Junction Temperature | TJMAX |  |  | 150 | °C |  | 2 |
| Thermal Resistance Junction to Case | θJC |  | 5 |  | °C/W | DD package | 2 |
| VPORT Operating Input Voltage (lower bound) | VPORT | 23 |  |  | V | At VPORT Pin | 3 |
| Signature/Class Hysteresis Window |  | 1 |  |  | V |  | 3 |
| Hot Swap On/Off Hysteresis Window |  | 3 |  |  | V |  | 3 |
| HSGATE Pull-Down Current |  | 200 |  |  | µA | VHSGATE, VHSSRC = 5V | 3 |

## CAD (KiCad official)

- Symbol: `LT4275AIDD#TRPBF`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `lt4275aidd-trpbf-etched.step` / `lt4275aidd-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt4275aidd-trpbf.step` / `lt4275aidd-trpbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/4275f.pdf) (12 pp, sha256 `3aab8b1d193cee44`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lt4275aidd-trpbf-datasheet.pdf)