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LT3845AEFE#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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LT3845AEFE#PBF
Analog Devices · DC-DC Converters · TSSOP-16-EP
LT3845AEFE#PBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Main supply pin, to be decoupled to SGND with a low ESR capacitor of at least 0.1µF located close to the pin; absolute maximum VIN is 65V and the operating range is 4V to 60V. |
| 2 | SHDN | input | Precision enable pin with a 1.35V rising threshold and 120mV hysteresis for UVLO; pulling it below 0.7V enters low-current shutdown, the pin is clamped to 6V, and its voltage rating is 5V with 1mA maximum pin current. |
| 3 | CSS | passive | Soft-start capacitor pin, where CSS = 2µA(tSS/1.231V) sets the output voltage slew rate; leave unconnected when soft-start is not used, and the voltage rating is 5V. |
| 4 | BURST_EN | input | Burst Mode enable pin where below 0.5V enables Burst Mode and reverse-current inhibit, above 0.5V disables Burst Mode, and reverse-current inhibit is disabled above 2.5V; the pin is rated 24V. |
| 5 | VFB | input | Output voltage feedback input connected to the supply output through a resistive divider, regulating at 1.231V, with a voltage rating of 5V. |
| 6 | VC | passive | Error amplifier output that sets the peak switch current and must not be pulled low by a low impedance source; if externally manipulated it must be driven through a 1kΩ series resistance, and the voltage rating is 5V. |
| 7 | SYNC | input | External clock input for oscillator synchronization, with RSET set so the internal oscillator runs 10% to 25% below the external clock within a 100kHz to 600kHz sync range; connect to SGND if unused, and the voltage rating is 5V. |
| 8 | fSET | passive | Oscillator frequency programming pin set by external resistor RSET, which is required even when an external sync clock is supplied; the programmable range is 100kHz to 500kHz. |
| 9 | SENSE- | input | Negative input of the current sense amplifier, connected to the VOUT side of the sense resistor in step-down applications; the pin is rated 40V and the differential sense voltage is limited to ±1V. |
| 10 | SENSE+ | input | Positive input of the current sense amplifier, connected to the inductor side of the sense resistor in step-down applications; the pin is rated 40V. |
| 11 | PGND | power_in | High-current ground reference for the internal low-side switch driver and VCC regulator, to be connected directly to the negative terminal of the VCC decoupling capacitor. |
| 12 | BG | output | Gate drive for the bottom N-channel MOSFET, to be routed with a short and wide trace (typically 0.02 in) to minimize inductance. |
| 13 | VCC | power_out | Internal bias supply decoupling node that requires a low ESR ceramic capacitor of 1µF or greater to PGND; the absolute maximum rating is 24V. |
| 14 | SW | passive | Reference for the VBOOST supply and high-current return for the bootstrapped switch; the switch voltage rating is 65V to -2V. |
| 15 | TG | output | Bootstrapped gate drive for the top N-channel MOSFET, to be routed with a short and wide trace (typically 0.02 in) to minimize inductance. |
| 16 | BOOST | power_out | Bootstrap supply for the gate drive, connected to a low ESR ceramic boost capacitor referenced to SW (0.1µF is typical); the maximum voltage seen is VIN + VCC, the BOOST-to-SW differential is limited to 24V, and the absolute maximum is 80V. |
| 17 | SGND | power_in | Exposed pad internally connected to the SGND low noise ground reference, which should be connected to the -VOUT side of the output capacitors and soldered to the PCB ground for thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16-EP |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage (VIN) | VIN | 65 | V | 2 | |||
| Switch voltage (SW) | SW | -2 | 65 | V | Note 8: -2 V is a transient condition | 2 | |
| SENSE+ and SENSE- voltages | 40 | V | 2 | ||||
| Differential sense voltage | -1 | 1 | V | SENSE+ to SENSE- | 2 | ||
| SYNC, VC, VFB, CSS and SHDN voltages | 5 | V | 2 | ||||
| SHDN pin currents | 1 | mA | 2 | ||||
| Operating junction temperature range (LT3845AE) | TJ | -40 | 125 | °C | LT3845AE (Note 3) | 2 | |
| Storage temperature | -65 | 150 | °C | 2 | |||
| Lead temperature (soldering) | 300 | °C | Soldering, 10 sec | 2 | |||
| Maximum junction temperature | TJMAX | 125 | °C | 2 | |||
| Junction-to-ambient thermal resistance | θJA | 40 | °C/W | 2 | |||
| Junction-to-case thermal resistance | θJC | 10 | °C/W | 2 | |||
| VIN operating voltage range | VIN | 4 | 60 | V | 3 | ||
| VIN minimum start voltage | 7.5 | V | 3 | ||||
| VIN UVLO threshold (falling) | 3.6 | 3.8 | V | 3 | |||
| VIN UVLO threshold hysteresis | 670 | mV | 3 | ||||
| VIN Burst Mode current | 20 | µA | VBURST_EN = 0V, VFB = 1.35V | 3 | |||
| VIN shutdown current | 9 | 15 | µA | VSHDN = 0V | 3 | ||
| BOOST operating voltage range | VBOOST, VSW | 5 | V | 3 | |||
| BOOST supply current | 1.4 | mA | Note 6 | 3 | |||
| BOOST Burst Mode current | 0.1 | µA | VBURST_EN = 0V | 3 | |||
| BOOST shutdown current | 0.1 | µA | VSHDN = 0V | 3 | |||
| VCC operating voltage range | VCC | 8 | V | Note 5 | 3 | ||
| VCC supply current | 3.7 | mA | Note 6 | 3 | |||
| VCC Burst Mode current | 100 | µA | VBURST_EN = 0V | 3 | |||
| VCC shutdown current | 20 | µA | VSHDN = 0V | 3 | |||
| Error amp reference voltage (full temperature range) | 1.215 | 1.231 | 1.245 | V | Measured at VFB pin; l = full operating temperature range | 3 | |
| Error amp reference voltage (TA = 25°C) | 1.224 | 1.231 | 1.238 | V | TA = 25°C; measured at VFB pin | 3 | |
| VFB pin input current | IVFB | 25 | nA | VFB = 1.231V | 3 | ||
| SHDN enable threshold (rising) | 1.3 | 1.35 | 1.4 | V | l = full operating temperature range | 3 | |
| SHDN threshold hysteresis | 120 | mV | 3 | ||||
| Sense pins common mode range | VSENSE+, VSENSE- | 0 | 36 | V | 3 | ||
| Current limit sense voltage | VSENSE+, VSENSE- | 90 | 100 | 115 | mV | VBURST_EN = VCC | 3 |
| Reverse protect sense voltage | VSENSE+, VSENSE- | -100 | mV | VBURST_EN = VCC | 3 | ||
| Reverse current inhibit offset | 10 | mV | VBURST_EN = 0V or VBURST_EN = VFB | 3 | |||
| Input current (ISENSE+ + ISENSE-) | 800 | µA | VSENSE(CM) = 0V | 3 | |||
| Input current (ISENSE+ + ISENSE-) | -20 | µA | VSENSE(CM) = 2V | 3 | |||
| Input current (ISENSE+ + ISENSE-) | -300 | µA | VSENSE(CM) > 4V | 3 | |||
| Operating frequency | 270 | 300 | 330 | kHz | l = full operating temperature range | 3 | |
| Minimum programmable frequency | 100 | kHz | l = full operating temperature range | 3 | |||
| Maximum programmable frequency | 500 | kHz | l = full operating temperature range | 3 | |||
| External sync frequency range | 100 | 600 | kHz | l = full operating temperature range | 3 | ||
| SYNC input resistance | 40 | kΩ | 3 | ||||
| SYNC voltage threshold | 1.4 | 2 | V | l = full operating temperature range | 3 | ||
| Soft-start capacitor control current | 2 | µA | 3 | ||||
| Error amp transconductance | 270 | 340 | 410 | µS | l = full operating temperature range | 3 | |
| Error amp DC voltage gain | 62 | dB | 3 | ||||
| Error amp sink/source current | -30 | 30 | µA | 3 | |||
| TG, BG drive on voltage | 9.8 | V | CLOAD = 3300pF; Note 7 | 4 | |||
| TG, BG drive off voltage | 0.1 | V | CLOAD = 3300pF | 4 | |||
| TG, BG drive rise/fall time | 50 | ns | 10% to 90% or 90% to 10%, CLOAD = 3300pF | 4 | |||
| Minimum TG off time | 350 | 650 | ns | l = full operating temperature range | 4 | ||
| Minimum TG on time | 250 | 400 | ns | l = full operating temperature range | 4 | ||
| Gate drive nonoverlap time (TG fall to BG rise) | 200 | ns | 4 | ||||
| Gate drive nonoverlap time (BG fall to TG rise) | 150 | ns | 4 |
CAD (KiCad official)
- Symbol:
LT3845AEFE#PBF - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lt3845aefe-pbf-etched.step/lt3845aefe-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3845aefe-pbf.step/lt3845aefe-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
6a4adebeb2ba3740, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).