component
LT3757IMSE#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT3757IMSE#PBF
Analog Devices · DC-DC Converters · MSOP-10-EP
LT3757IMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VC | passive | Error amplifier compensation pin used to stabilize the voltage loop with an external RC network. |
| 2 | FBX | input | Positive and negative feedback pin that receives the feedback voltage from the external resistor divider across the output, regulated at 1.6V (positive) or -0.8V (negative), and also modulates frequency during start-up and faults when FBX is close to GND. |
| 3 | SS | passive | Soft-start pin with a 10µA (typical) pull-up to an internal 2.5V rail that sets the soft-start interval via an external capacitor and is reset to GND by UVLO, INTVCC under/overvoltage, or thermal lockout. |
| 4 | RT | passive | Switching frequency adjustment pin; set the frequency with a resistor to GND, and do not leave this pin open. |
| 5 | SYNC | input | Frequency synchronization pin; choose the RT resistor for a switching frequency 20% slower than the SYNC pulse frequency, and tie to GND if unused (ignored when FBX is close to GND). |
| 6 | SENSE | input | Current sense input for the control loop, Kelvin connected to the positive terminal of the N-channel MOSFET source sense resistor, with its negative terminal tied to the GND plane close to the IC. |
| 7 | GATE | output | N-channel MOSFET gate driver output that switches between INTVCC and GND, and is driven to GND when the IC is shut down, in thermal lockout, or when INTVCC is outside its OV/UV thresholds. |
| 8 | INTVCC | power_out | Regulated 7.2V (typical) supply for internal loads and gate driver that must be bypassed with at least 4.7µF close to the pin; it may connect directly to VIN if VIN is below 17.5V and must not exceed 17.5V when driven externally. |
| 9 | SHDN/UVLO | input | Shutdown and undervoltage detect pin with an accurate 1.22V (nominal) falling threshold; tie to 0.4V or less to disable the device and reduce VIN quiescent current below 1µA. |
| 10 | VIN | power_in | Input supply pin that must be locally bypassed with a 0.22µF or larger capacitor placed close to the pin; operating range is 2.9V to 40V. |
| 11 | GND | power_in | Exposed pad ground that also serves as the negative terminal of the current sense resistor and must be soldered directly to the local ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10-EP |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Range | VIN | 2.9 | 40 | V | 3 | ||
| VIN Shutdown IQ | IQ | 0.1 | 1 | µA | SHDN/UVLO = 0V | 3 | |
| VIN Shutdown IQ | IQ | 6 | µA | SHDN/UVLO = 1.15V | 3 | ||
| VIN Operating IQ | IQ | 1.6 | 2.2 | mA | VC = 0.3V, RT = 41.2k | 3 | |
| VIN Operating IQ with Internal LDO Disabled | IQ | 280 | 400 | µA | VC = 0.3V, RT = 41.2k, INTVCC = 7.5V | 3 | |
| SENSE Current Limit Threshold | 100 | 110 | 120 | mV | Over full operating temperature range (l) | 3 | |
| SENSE Input Bias Current | -65 | µA | Current out of pin | 3 | |||
| FBX Regulation Voltage (VFBX(REG)) | VFBX(REG) | 1.569 | 1.6 | 1.631 | V | VFBX > 0V (Note 3); over full operating temperature range (l) | 3 |
| FBX Regulation Voltage (VFBX(REG)) | VFBX(REG) | -0.816 | -0.8 | -0.784 | V | VFBX < 0V (Note 3); over full operating temperature range (l) | 3 |
| FBX Overvoltage Lockout | 6 | 8 | 10 | % | VFBX > 0V (Note 4) | 3 | |
| FBX Overvoltage Lockout | 7 | 11 | 14 | % | VFBX < 0V (Note 4) | 3 | |
| FBX Pin Input Current | 70 | 100 | nA | VFBX = 1.6V (Note 3) | 3 | ||
| FBX Pin Input Current | -10 | 10 | nA | VFBX = -0.8V (Note 3) | 3 | ||
| VFBX Line Regulation | 0.002 | 0.056 | %/V | VFBX > 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 | ||
| VFBX Line Regulation | 0.0025 | 0.05 | %/V | VFBX < 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 | ||
| Switching Frequency | 270 | 300 | 330 | kHz | RT = 41.2k to GND, VFBX = 1.6V | 3 | |
| INTVCC Regulation Voltage | INTVCC | 7 | 7.2 | 7.4 | V | Over full operating temperature range (l) | 3 |
| INTVCC Undervoltage Lockout Threshold | INTVCC | 2.6 | 2.7 | 2.8 | V | Falling INTVCC | 3 |
| INTVCC Overvoltage Lockout Threshold | INTVCC | 16 | 17.5 | V | 3 | ||
| INTVCC Current Limit | 30 | 40 | 55 | mA | VIN = 40V | 3 | |
| INTVCC Load Regulation | -0.9 | -0.5 | % | 0 < IINTVCC < 20mA, VIN = 8V | 3 | ||
| INTVCC Line Regulation | 0.008 | 0.03 | %/V | 8V < VIN < 40V | 3 | ||
| SHDN/UVLO Threshold Voltage Falling | 1.17 | 1.22 | 1.27 | V | VIN = INTVCC = 8V; over full operating temperature range (l) | 4 | |
| SHDN/UVLO Pin Bias Current Low | 1.7 | 2 | 2.5 | µA | SHDN/UVLO = 1.15V | 4 | |
| SHDN/UVLO Pin Bias Current High | 10 | 100 | nA | SHDN/UVLO = 1.30V | 4 | ||
| SENSE pin voltage (Absolute Maximum) | SENSE | -0.3 | 0.3 | V | 2 | ||
| VIN, SHDN/UVLO Absolute Maximum | VIN, SHDN/UVLO | 40 | V | Note 6 | 2 | ||
| INTVCC Absolute Maximum | INTVCC | 20 | V | Printed as VIN + 0.3V, 20V | 2 | ||
| SYNC Absolute Maximum | SYNC | 8 | V | 2 | |||
| VC, SS Absolute Maximum | VC, SS | 3 | V | 2 | |||
| RT Absolute Maximum | RT | 1.5 | V | 2 | |||
| FBX Absolute Maximum | FBX | -6 | 6 | V | Note 1 | 2 | |
| Operating Temperature Range | -40 | 125 | °C | LT3757I / LT3757AI (MSOP), Notes 2, 8 | 2 | ||
| Storage Temperature Range (MSOP) | -65 | 150 | °C | MSOP | 2 | ||
| Lead Temperature (Soldering, 10 sec) (MSOP) | 300 | °C | Soldering, 10 sec, MSOP | 2 | |||
| Maximum Junction Temperature (TJMAX) | TJMAX | 150 | °C | MSE package | 2 | ||
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | 40 | °C/W | MSE package, exposed pad soldered to PCB | 2 |
CAD (KiCad official)
- Symbol:
LT3757IMSE#PBF - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files:
lt3757imse-pbf-etched.step/lt3757imse-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3757imse-pbf.step/lt3757imse-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
1f145722dfa27e74, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT3757IMSE#PBF
**Analog Devices** · DC-DC Converters · MSOP-10-EP
LT3757IMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VC | passive | Error amplifier compensation pin used to stabilize the voltage loop with an external RC network. |
| 2 | FBX | input | Positive and negative feedback pin that receives the feedback voltage from the external resistor divider across the output, regulated at 1.6V (positive) or -0.8V (negative), and also modulates frequency during start-up and faults when FBX is close to GND. |
| 3 | SS | passive | Soft-start pin with a 10µA (typical) pull-up to an internal 2.5V rail that sets the soft-start interval via an external capacitor and is reset to GND by UVLO, INTVCC under/overvoltage, or thermal lockout. |
| 4 | RT | passive | Switching frequency adjustment pin; set the frequency with a resistor to GND, and do not leave this pin open. |
| 5 | SYNC | input | Frequency synchronization pin; choose the RT resistor for a switching frequency 20% slower than the SYNC pulse frequency, and tie to GND if unused (ignored when FBX is close to GND). |
| 6 | SENSE | input | Current sense input for the control loop, Kelvin connected to the positive terminal of the N-channel MOSFET source sense resistor, with its negative terminal tied to the GND plane close to the IC. |
| 7 | GATE | output | N-channel MOSFET gate driver output that switches between INTVCC and GND, and is driven to GND when the IC is shut down, in thermal lockout, or when INTVCC is outside its OV/UV thresholds. |
| 8 | INTVCC | power_out | Regulated 7.2V (typical) supply for internal loads and gate driver that must be bypassed with at least 4.7µF close to the pin; it may connect directly to VIN if VIN is below 17.5V and must not exceed 17.5V when driven externally. |
| 9 | SHDN/UVLO | input | Shutdown and undervoltage detect pin with an accurate 1.22V (nominal) falling threshold; tie to 0.4V or less to disable the device and reduce VIN quiescent current below 1µA. |
| 10 | VIN | power_in | Input supply pin that must be locally bypassed with a 0.22µF or larger capacitor placed close to the pin; operating range is 2.9V to 40V. |
| 11 | GND | power_in | Exposed pad ground that also serves as the negative terminal of the current sense resistor and must be soldered directly to the local ground plane. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10-EP |
| Category | Power Management (PMIC) |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Range | VIN | 2.9 | | 40 | V | | 3 |
| VIN Shutdown IQ | IQ | | 0.1 | 1 | µA | SHDN/UVLO = 0V | 3 |
| VIN Shutdown IQ | IQ | | | 6 | µA | SHDN/UVLO = 1.15V | 3 |
| VIN Operating IQ | IQ | | 1.6 | 2.2 | mA | VC = 0.3V, RT = 41.2k | 3 |
| VIN Operating IQ with Internal LDO Disabled | IQ | | 280 | 400 | µA | VC = 0.3V, RT = 41.2k, INTVCC = 7.5V | 3 |
| SENSE Current Limit Threshold | | 100 | 110 | 120 | mV | Over full operating temperature range (l) | 3 |
| SENSE Input Bias Current | | | | -65 | µA | Current out of pin | 3 |
| FBX Regulation Voltage (VFBX(REG)) | VFBX(REG) | 1.569 | 1.6 | 1.631 | V | VFBX > 0V (Note 3); over full operating temperature range (l) | 3 |
| FBX Regulation Voltage (VFBX(REG)) | VFBX(REG) | -0.816 | -0.8 | -0.784 | V | VFBX < 0V (Note 3); over full operating temperature range (l) | 3 |
| FBX Overvoltage Lockout | | 6 | 8 | 10 | % | VFBX > 0V (Note 4) | 3 |
| FBX Overvoltage Lockout | | 7 | 11 | 14 | % | VFBX < 0V (Note 4) | 3 |
| FBX Pin Input Current | | | 70 | 100 | nA | VFBX = 1.6V (Note 3) | 3 |
| FBX Pin Input Current | | -10 | | 10 | nA | VFBX = -0.8V (Note 3) | 3 |
| VFBX Line Regulation | | | 0.002 | 0.056 | %/V | VFBX > 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 |
| VFBX Line Regulation | | | 0.0025 | 0.05 | %/V | VFBX < 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 |
| Switching Frequency | | 270 | 300 | 330 | kHz | RT = 41.2k to GND, VFBX = 1.6V | 3 |
| INTVCC Regulation Voltage | INTVCC | 7 | 7.2 | 7.4 | V | Over full operating temperature range (l) | 3 |
| INTVCC Undervoltage Lockout Threshold | INTVCC | 2.6 | 2.7 | 2.8 | V | Falling INTVCC | 3 |
| INTVCC Overvoltage Lockout Threshold | INTVCC | 16 | 17.5 | | V | | 3 |
| INTVCC Current Limit | | 30 | 40 | 55 | mA | VIN = 40V | 3 |
| INTVCC Load Regulation | | -0.9 | | -0.5 | % | 0 < IINTVCC < 20mA, VIN = 8V | 3 |
| INTVCC Line Regulation | | | 0.008 | 0.03 | %/V | 8V < VIN < 40V | 3 |
| SHDN/UVLO Threshold Voltage Falling | | 1.17 | 1.22 | 1.27 | V | VIN = INTVCC = 8V; over full operating temperature range (l) | 4 |
| SHDN/UVLO Pin Bias Current Low | | 1.7 | 2 | 2.5 | µA | SHDN/UVLO = 1.15V | 4 |
| SHDN/UVLO Pin Bias Current High | | | 10 | 100 | nA | SHDN/UVLO = 1.30V | 4 |
| SENSE pin voltage (Absolute Maximum) | SENSE | -0.3 | | 0.3 | V | | 2 |
| VIN, SHDN/UVLO Absolute Maximum | VIN, SHDN/UVLO | | | 40 | V | Note 6 | 2 |
| INTVCC Absolute Maximum | INTVCC | | | 20 | V | Printed as VIN + 0.3V, 20V | 2 |
| SYNC Absolute Maximum | SYNC | | | 8 | V | | 2 |
| VC, SS Absolute Maximum | VC, SS | | | 3 | V | | 2 |
| RT Absolute Maximum | RT | | | 1.5 | V | | 2 |
| FBX Absolute Maximum | FBX | -6 | | 6 | V | Note 1 | 2 |
| Operating Temperature Range | | -40 | | 125 | °C | LT3757I / LT3757AI (MSOP), Notes 2, 8 | 2 |
| Storage Temperature Range (MSOP) | | -65 | | 150 | °C | MSOP | 2 |
| Lead Temperature (Soldering, 10 sec) (MSOP) | | | | 300 | °C | Soldering, 10 sec, MSOP | 2 |
| Maximum Junction Temperature (TJMAX) | TJMAX | | | 150 | °C | MSE package | 2 |
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | | 40 | | °C/W | MSE package, exposed pad soldered to PCB | 2 |
## CAD (KiCad official)
- Symbol: `LT3757IMSE#PBF`
- Footprint: `Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm`
- 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files: `lt3757imse-pbf-etched.step` / `lt3757imse-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt3757imse-pbf.step` / `lt3757imse-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883396206735360) (36 pp, sha256 `1f145722dfa27e74`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt3757imse-pbf-datasheet.pdf)