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LT3757EMSE#PBF

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Analog Devices AC-DC Controllers & Regulators, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT3757EMSE#PBF

Analog Devices · AC-DC Controllers & Regulators · MSOP-10-EP

LT3757EMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VC passive Error amplifier compensation pin used to stabilize the voltage loop with an external RC network, with a 5.5 V/V current mode gain and a 5 MΩ output impedance stated in the electrical characteristics; absolute maximum rating is 3 V.
2 FBX input Positive and negative feedback pin that receives the divider voltage from the output, regulated to 1.6 V (positive) or -0.8 V (negative), with an absolute maximum range of -6 V to 6 V.
3 SS passive Soft-start pin that sets the soft-start interval with an external capacitor and has a 10 µA (typical) pull-up to an internal 2.5 V rail; it is reset to GND by UVLO, INTVCC UV/OV or thermal lockout.
4 RT passive Switching frequency adjustment pin where a resistor to GND sets the frequency from 50 kHz to 1 MHz, with RT voltage of 1.2 V and an absolute maximum of 1.5 V, and it must not be left open.
5 SYNC input Frequency synchronization pin for an external clock, where the RT resistor must be chosen for a switching frequency 20% slower than the SYNC pulse frequency, input low is 0.4 V max, input high is 1.5 V min, and it must be tied to GND if unused.
6 SENSE input Current sense input for the control loop that must be Kelvin connected to the positive terminal of the switch current sense resistor, with an absolute maximum range of ±0.3 V and a 110 mV (typical) current limit threshold.
7 GATE output N-channel MOSFET gate driver output that switches between INTVCC and GND and is driven to GND during shutdown, thermal lockout, or INTVCC over/undervoltage faults.
8 INTVCC power_out Regulated supply for internal loads and the gate driver, regulated to 7.2 V (typical) and requiring a minimum 4.7 µF bypass capacitor placed close to the pin, with an absolute maximum of VIN + 0.3 V or 20 V.
9 SHDN/UVLO input Shutdown and undervoltage detect pin with an accurate 1.22 V (nominal) falling threshold, where tying it to 0.4 V or less disables the device and reduces VIN quiescent current below 1 µA, and its absolute maximum is 40 V.
10 VIN power_in Input supply pin operating from 2.9 V to 40 V, which must be locally bypassed with a 0.22 µF or larger capacitor placed close to the pin.
11 GND power_in Ground exposed pad that also serves as the negative terminal of the current sense resistor and must be soldered directly to the local ground plane.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10-EP
Category Power Management ICs
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN Operating Range VIN 2.9 40 V 3
FBX Regulation Voltage (VFBX > 0V) VFBX(REG) 1.569 1.6 1.631 V VFBX > 0V 3
FBX Regulation Voltage (VFBX < 0V) VFBX(REG) -0.816 -0.8 -0.784 V VFBX < 0V 3
SENSE Current Limit Threshold VSENSE(MAX) 100 110 120 mV 3
FBX Overvoltage Lockout (VFBX > 0V) 6 8 11 % VFBX > 0V 3
FBX Overvoltage Lockout (VFBX < 0V) 7 10 14 % VFBX < 0V 3
FBX Pin Input Current -10 10 nA VFBX = 1.6V 3
FBX Pin Input Current 70 100 nA VFBX = -0.8V 3
VFBX Line Regulation (VFBX > 0V) 0.002 0.0025 %/V VFBX > 0V, 2.9V < VIN < 40V 3
VFBX Line Regulation (VFBX < 0V) 0.05 0.056 %/V VFBX < 0V, 2.9V < VIN < 40V 3
VIN Shutdown IQ IQ 0.1 1 µA SHDN/UVLO = 0V 3
VIN Shutdown IQ IQ 6 µA SHDN/UVLO = 1.15V 3
VIN Operating IQ IQ 1.6 2.2 mA VC = 0.3V, RT = 41.2k 3
VIN Operating IQ with Internal LDO Disabled IQ 280 400 µA VC = 0.3V, RT = 41.2k, INTVCC = 7.5V 3
Switching Frequency (RT = 41.2k) fSW 270 300 330 kHz RT = 41.2k to GND, VFBX = 1.6V 3
SYNC Input Low 0.4 V 4
SYNC Input High 1.5 V 4
INTVCC Regulation Voltage INTVCC 7 7.2 7.4 V 4
INTVCC Undervoltage Lockout Threshold (Falling) 2.6 2.7 2.8 V Falling INTVCC 4
INTVCC Overvoltage Lockout Threshold 16 17.5 V 4
INTVCC Current Limit 30 40 55 mA VIN = 40V 4
INTVCC Load Regulation ΔVINTVCC/VINTVCC -0.9 -0.5 % 0 < IINTVCC < 20mA, VIN = 8V 4
INTVCC Line Regulation ΔVINTVCC/(VINTVCC • ΔVIN) 0.008 0.03 %/V 8V < VIN < 40V 4
Dropout Voltage (VIN - VINTVCC) 400 mV VIN = 6V, IINTVCC = 20mA 4
SHDN/UVLO Threshold Voltage (Falling) 1.17 1.22 1.27 V VIN = INTVCC = 8V 4
SHDN/UVLO Input Low Voltage 0.4 V I(VIN) drops below 1µA 4
SHDN/UVLO Pin Bias Current Low 1.7 2 2.5 µA SHDN/UVLO = 1.15V 4
Gate VOL 0.05 V 4
VIN, SHDN/UVLO (absolute maximum) VIN, SHDN/UVLO 40 V Note 6: for VIN below 6V, SHDN/UVLO must not exceed VIN 2
INTVCC (absolute maximum) INTVCC 20 V Also VIN + 0.3V 2
SYNC (absolute maximum) SYNC 8 V 2
VC, SS (absolute maximum) VC, SS 3 V 2
RT (absolute maximum) RT 1.5 V 2
SENSE (absolute maximum) SENSE -0.3 0.3 V 2
FBX (absolute maximum) FBX -6 6 V Note 1 2
Storage Temperature Range (MSOP) TSTG -65 150 °C MSOP package 2
Lead Temperature (Soldering, 10 sec) (MSOP) 300 °C MSOP package 2
Operating Temperature Range (E grade) -40 125 °C LT3757E/LT3757AE; Notes 2, 8 2
Maximum Junction Temperature (MSE package) TJMAX 150 °C MSE package 2
Thermal Resistance Junction-to-Ambient (MSE package) θJA 40 °C/W MSE package, exposed pad soldered to full copper plane 10
SENSE Input Bias Current -65 µA Current out of pin 3
VC Source Current -15 µA VFBX = 0V, VC = 1.5V 3
VC Sink Current 12 µA VFBX = 1.7V 3
VC Sink Current 11 µA VFBX = -0.85V 3
Transconductance gm gm 230 µS ΔIVC/ΔVFBX, Note 3 3
VC Output Impedance 5 MΩ Note 3 3
VC Current Mode Gain ΔVVC/ΔVSENSE 5.5 V/V 3
Switching Frequency (RT = 442k) fSW 50 kHz RT = 442k to GND, VFBX = 1.6V 3
Switching Frequency (RT = 10.5k) fSW 1000 kHz RT = 10.5k to GND, VFBX = 1.6V 3
RT Voltage VRT 1.2 V VFBX = 1.6V 3
Minimum Off-Time 220 ns 3
Minimum On-Time 220 ns 3
SS Pull-Up Current -10 µA SS = 0V, current out of pin 4
INTVCC UVLO Hysteresis 0.1 V 4
INTVCC Current Limit 95 mA VIN = 15V 4
Dropout Current in Shutdown (INTVCC) 16 µA SHDN/UVLO = 0V, INTVCC = 8V 4
INTVCC Voltage to Bypass Internal LDO 7.5 V 4
SHDN/UVLO Pin Bias Current High 10 100 nA SHDN/UVLO = 1.30V 4
Gate Driver Output Rise Time tr 22 ns CL = 3300pF, INTVCC = 7.5V 4
Gate Driver Output Fall Time tf 20 ns CL = 3300pF, INTVCC = 7.5V 4

CAD (KiCad official)

  • Symbol: LT3757EMSE#PBF
  • Footprint: Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm
  • 3D model: MSOP-10-EP (KiCad packages3D, STEP)
  • 3D model files: lt3757emse-pbf-etched.step / lt3757emse-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3757emse-pbf.step / lt3757emse-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (38 pp, sha256 a50e40555a5ca7a0, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF