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LT3757AEMSE#PBF
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Analog Devices DC-DC Controllers, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLT3757AEMSE#PBF
Analog Devices · DC-DC Controllers · MSOP-10-EP
LT3757AEMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VC | passive | Error amplifier compensation pin used to stabilize the voltage loop with an external RC network. |
| 2 | FBX | input | Positive and negative feedback pin receiving the output divider voltage (regulates to 1.6V or -0.8V, absolute max -6V to 6V), and modulates frequency during start-up and fault when close to GND. |
| 3 | SS | passive | Soft-start pin with 10µA (typical) pull-up to an internal 2.5V rail; an external capacitor sets the soft-start interval (absolute max 3V). |
| 4 | RT | passive | Switching frequency adjustment pin; set frequency (50kHz to 1MHz) with a resistor to GND and do not leave open (absolute max 1.5V). |
| 5 | SYNC | input | Frequency synchronization input for an external clock with RT set 20% slower than the SYNC frequency; tie to GND if unused (absolute max 8V). |
| 6 | SENSE | input | Current sense input for the control loop, Kelvin connected to the positive terminal of the switch current sense resistor (absolute max ±0.3V, 110mV typical current limit threshold). |
| 7 | GATE | output | N-channel MOSFET gate driver output switching between INTVCC and GND, driven to GND in shutdown, thermal lockout or INTVCC UV/OV. |
| 8 | INTVCC | power_out | Regulated 7.2V (typical) supply for internal loads and gate driver, requires a minimum 4.7µF bypass capacitor and can be tied to VIN if VIN is below 17.5V. |
| 9 | SHDN/UVLO | input | Shutdown and undervoltage detect pin with accurate 1.22V falling threshold and programmable hysteresis; tie to 0.4V or less to disable and reduce VIN quiescent current below 1µA. |
| 10 | VIN | power_in | Input supply pin (2.9V to 40V operating range) that must be locally bypassed with a 0.22µF or larger capacitor close to the pin. |
| 11 | GND | power_in | Exposed pad ground that also serves as the negative terminal of the current sense resistor and must be soldered directly to the local ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10-EP |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Range | VIN | 2.9 | 40 | V | 3 | ||
| VIN Shutdown IQ | IQ | 0.1 | 1 | µA | SHDN/UVLO = 0V | 3 | |
| VIN Shutdown IQ | IQ | 6 | µA | SHDN/UVLO = 1.15V | 3 | ||
| VIN Operating IQ | IQ | 1.6 | 2.2 | mA | VC = 0.3V, RT = 41.2k | 3 | |
| VIN Operating IQ with Internal LDO Disabled | IQ | 280 | 400 | µA | VC = 0.3V, RT = 41.2k, INTVCC = 7.5V | 3 | |
| SENSE Current Limit Threshold | 100 | 110 | 120 | mV | 3 | ||
| SENSE Input Bias Current | -65 | µA | Current Out of Pin | 3 | |||
| FBX Regulation Voltage | VFBX(REG) | 1.569 | 1.6 | 1.631 | V | VFBX > 0V (Note 3) | 3 |
| FBX Regulation Voltage | VFBX(REG) | -0.816 | -0.8 | -0.784 | V | VFBX < 0V (Note 3) | 3 |
| FBX Overvoltage Lockout | 6 | 8 | 10 | % | VFBX > 0V (Note 4) | 3 | |
| FBX Overvoltage Lockout | 7 | 11 | 14 | % | VFBX < 0V (Note 4) | 3 | |
| FBX Pin Input Current | 70 | 100 | nA | VFBX = 1.6V (Note 3) | 3 | ||
| FBX Pin Input Current | -10 | 10 | nA | VFBX = -0.8V (Note 3) | 3 | ||
| Transconductance | gm | 230 | µS | (Note 3) | 3 | ||
| VC Output Impedance | 5 | MΩ | (Note 3) | 3 | |||
| VFBX Line Regulation | 0.002 | 0.056 | %/V | VFBX > 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 | ||
| VFBX Line Regulation | 0.0025 | 0.05 | %/V | VFBX < 0V, 2.9V < VIN < 40V (Notes 3, 7) | 3 | ||
| VC Current Mode Gain | 5.5 | V/V | 3 | ||||
| VC Source Current | -15 | µA | VFBX = 0V, VC = 1.5V | 3 | |||
| VC Sink Current | 12 | µA | VFBX = 1.7V | 3 | |||
| VC Sink Current | 11 | µA | VFBX = -0.85V | 3 | |||
| Switching Frequency | 270 | 300 | 330 | kHz | RT = 41.2k to GND, VFBX = 1.6V | 3 | |
| Switching Frequency | 50 | kHz | RT = 442k to GND, VFBX = 1.6V | 3 | |||
| Switching Frequency | 1000 | kHz | RT = 10.5k to GND, VFBX = 1.6V | 3 | |||
| RT Voltage | 1.2 | V | VFBX = 1.6V | 3 | |||
| Minimum Off-Time | 220 | ns | 3 | ||||
| Minimum On-Time | 220 | ns | 3 | ||||
| SYNC Input Low | 0.4 | V | 4 | ||||
| SYNC Input High | 1.5 | V | 4 | ||||
| SS Pull-Up Current | -10 | µA | SS = 0V, Current Out of Pin | 4 | |||
| INTVCC Regulation Voltage | 7 | 7.2 | 7.4 | V | 4 | ||
| INTVCC Undervoltage Lockout Threshold | 2.6 | 2.7 | 2.8 | V | Falling INTVCC | 4 | |
| INTVCC UVLO Hysteresis | 0.1 | V | 4 | ||||
| INTVCC Overvoltage Lockout Threshold | 16 | 17.5 | V | 4 | |||
| INTVCC Current Limit | 30 | 40 | 55 | mA | VIN = 40V | 4 | |
| INTVCC Current Limit | 95 | mA | VIN = 15V | 4 | |||
| INTVCC Load Regulation | ∆VINTVCC/VINTVCC | -0.9 | -0.5 | % | 0 < IINTVCC < 20mA, VIN = 8V | 4 | |
| INTVCC Line Regulation | 0.008 | 0.03 | %/V | 8V < VIN < 40V | 4 | ||
| Dropout Voltage (VIN, VINTVCC) | 400 | mV | VIN = 6V, IINTVCC = 20mA | 4 | |||
| INTVCC Current in Shutdown | 16 | µA | SHDN/UVLO = 0V, INTVCC = 8V | 4 | |||
| INTVCC Voltage to Bypass Internal LDO | 7.5 | V | 4 | ||||
| SHDN/UVLO Threshold Voltage Falling | 1.17 | 1.22 | 1.27 | V | VIN = INTVCC = 8V | 4 | |
| SHDN/UVLO Input Low Voltage | 0.4 | V | I(VIN) Drops Below 1µA | 4 | |||
| SHDN/UVLO Pin Bias Current Low | 1.7 | 2 | 2.5 | µA | SHDN/UVLO = 1.15V | 4 | |
| SHDN/UVLO Pin Bias Current High | 10 | 100 | nA | SHDN/UVLO = 1.30V | 4 | ||
| Gate Driver Output Rise Time | tr | 22 | ns | CL = 3300pF (Note 5), INTVCC = 7.5V | 4 | ||
| Gate Driver Output Fall Time | tf | 20 | ns | CL = 3300pF (Note 5), INTVCC = 7.5V | 4 | ||
| Gate VOL | VOL | 0.05 | V | 4 | |||
| VIN, SHDN/UVLO Voltage | VIN | 40 | V | VIN, SHDN/UVLO (Note 6) | 2 | ||
| INTVCC Voltage | INTVCC | 20 | V | VIN + 0.3V, 20V | 2 | ||
| SYNC Voltage | SYNC | 8 | V | 2 | |||
| VC, SS Voltage | 3 | V | 2 | ||||
| RT Voltage | RT | 1.5 | V | 2 | |||
| SENSE Voltage | SENSE | -0.3 | 0.3 | V | 2 | ||
| FBX Voltage | FBX | -6 | 6 | V | 2 | ||
| Operating Temperature Range | -40 | 125 | °C | LT3757AE (Notes 2, 8) | 2 | ||
| Storage Temperature Range | -65 | 150 | °C | MSOP | 2 | ||
| Lead Temperature (Soldering, 10 sec) | 300 | °C | MSOP | 2 | |||
| Maximum Junction Temperature | TJMAX | 150 | °C | MSE package | 2 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 40 | °C/W | MSE package | 2 |
CAD (KiCad official)
- Symbol:
LT3757AEMSE#PBF - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files:
lt3757aemse-pbf-etched.step/lt3757aemse-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3757aemse-pbf.step/lt3757aemse-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (38 pp, sha256
a50e40555a5ca7a0, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).