component

LT3742EUF#PBF

Public Made by Adom

by adom

Analog Devices DC-DC Converters, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslt3742euf#pbffactory-2.0.0extractor-text

Verified LT3742EUF#PBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT3742EUF#PBF · QFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 26-page datasheet
  • ✓distributor: lcsc C671338, digikey 505-LT3742EUF#PBF-ND, mouser 584-LT3742EUF#PBF
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5m7o2k6e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.24)
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt3742euf-pbf.kicad_sym✓ lt3742euf-pbf.kicad_mod✓ lt3742euf-pbf.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
lt3742euf-pbf / README.md
History Download
Ray Publish 0.1.0 adc0219 8d ago

LT3742EUF#PBF

Analog Devices · DC-DC Converters · QFN-24-EP(4x4)

LT3742EUF#PBF from Analog Devices, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G1 output Gate drive output for controller 1's external N-channel MOSFET, a floating driver whose voltage swings between the BIAS and SW pins.
2 VIN power_in Input voltage pin supplying the internal circuitry (4V to 30V operating, 30V abs max); must be locally bypassed with a capacitor.
3 UVLO input Undervoltage lockout input with 1.25V threshold programmed by a divider from VIN, 3µA hysteresis current sink; do not leave open, connect to VIN if unused.
4 BIAS passive Gate-drive bias rail regulated to VIN + 7V to drive the external N-channel MOSFETs (40V abs max).
5 SWB output Collector of the internal NPN switch of the bias boost regulator that generates the gate-drive bias voltage (40V abs max, 340mA typ current limit).
6 G2 output Gate drive output for controller 2's external N-channel MOSFET, a floating driver whose voltage swings between the BIAS and SW pins.
7 SW2 passive Switch node of regulator 2, connected to the source of the external N-channel MOSFET and to the inductor and diode.
8 NC unconnected No connect pin.
9 NC unconnected No connect pin.
10 SENSE2+ input Positive current sense input of regulator 2, used with SENSE2- to sense inductor current (30V abs max).
11 SENSE2- input Negative current sense input of regulator 2, used with SENSE2+ to sense inductor current (30V abs max).
12 FB2 input Feedback pin of regulator 2, regulated to 800mV; connect feedback resistors here to set the output voltage.
13 VC2 passive Control voltage and error amplifier compensation pin for regulator 2; connect a series RC to ground.
14 PG2 output Open-collector power good output for regulator 2, low until FB is within 90% of final regulation; leave unconnected if unused.
15 RUN/SS2 input Run/soft-start pin for regulator 2; pull to ground with an open-drain device to shut down, add a capacitor for soft-start (1µA charge current).
16 RUN/SS1 input Run/soft-start pin for regulator 1; pull to ground with an open-drain device to shut down, add a capacitor for soft-start (1µA charge current).
17 PG1 output Open-collector power good output for regulator 1, low until FB is within 90% of final regulation; leave unconnected if unused.
18 VC1 passive Control voltage and error amplifier compensation pin for regulator 1; connect a series RC to ground.
19 FB1 input Feedback pin of regulator 1, regulated to 800mV; connect feedback resistors here to set the output voltage.
20 SENSE1- input Negative current sense input of regulator 1, used with SENSE1+ to sense inductor current (30V abs max).
21 SENSE1+ input Positive current sense input of regulator 1, used with SENSE1- to sense inductor current (30V abs max).
22 NC unconnected No connect pin.
23 NC unconnected No connect pin.
24 SW1 passive Switch node of regulator 1, connected to the source of the external N-channel MOSFET and to the inductor and diode.
25 GND power_in Exposed pad, ground; provides electrical and thermal contact to the PCB and must be soldered to the board.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package QFN-24-EP(4x4)
Category Power Management ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage VIN 30 V 2
UVLO Voltage 30 V 2
PG1, PG2 Voltage 30 V 2
SWB, BIAS Voltage 40 V 2
SENSE+ Voltage 30 V SENSE1+, SENSE2+ 2
SENSE- Voltage 30 V SENSE1-, SENSE2- 2
RUN/SS Voltage 6 V RUN/SS1, RUN/SS2 2
FB Voltage 6 V FB1, FB2 2
VC Voltage 6 V VC1, VC2 2
Junction Temperature TJMAX 125 °C 2
Operating Junction Temperature Range TJ -40 125 °C Note 2 2
Storage Temperature Range TSTG -65 125 °C 2
Junction-to-Ambient Thermal Resistance θJA 36 °C/W UF package 2
Minimum Operating Input Voltage 3.5 4 V VUVLO = 1.5V 2
Quiescent Current IQ 5 7 mA VRUN/SS1 = VRUN/SS2 = VFB1 = VFB2 = 1V 2
Shutdown Current 20 35 µA VRUN/SS1 = VRUN/SS2 = 0V 2
UVLO Pin Threshold 1.2 1.25 1.28 V UVLO Pin Voltage Rising 2
UVLO Pin Hysteresis Current 1.8 3 4 µA VUVLO = 1V, Current Flows Into Pin 2
RUN/SS Pin Threshold 0.2 0.5 V 2
RUN/SS Pin Charge Current 0.5 1 1.5 µA VRUN/SS = 0V 2
FB Pin Voltage VFB 0.788 0.8 0.812 V 2
FB Pin Bias Current 50 200 nA VFB = 0.8V, VC = 0.4V 3
FB Pin Voltage Matching -4 0 4 mV 3
Controller Switching Frequency 440 500 560 kHz 3
Maximum Current Sense Voltage 50 60 70 mV VSENSE- = 3.3V 3
Current Sense Matching Between Controllers 5 % printed ±5 3
Gate On Voltage (VG, VSW) 6 6.7 7 V VBIAS = 12V 3
Gate Off Voltage (VG, VSW) 0.4 0.75 V VBIAS = 12V 3
PG Pin Voltage Low 0.2 0.5 V IPG = 100µA 3
Lower PG Trip Level -13 -10 -7 % Relative to VFB, VFB Increasing 3
Lower PG Trip Level -16 -13 -10 % Relative to VFB, VFB Decreasing 3
Upper PG Trip Level 7 10 13 % Relative to VFB, VFB Increasing 3
Upper PG Trip Level 4 7 10 % Relative to VFB, VFB Decreasing 3
PG Pin Leakage Current 0.1 µA VPG = 2V 3
PG Pin Sink Current 200 500 µA VPG = 0.5V 3
Bias Pin Voltage 6.6 7 7.7 V relative to VIN (VIN + x) 3
SWB Pin Current Limit 250 340 500 mA 3
SWB Pin Leakage Current 0.01 1 µA VSWB = 12V 3
Bias Supply Switching Frequency 0.88 1 1.12 MHz 3
FB Pin Voltage Line Regulation 0.01 %/V VIN = 5V to 30V 2
Error Amplifier Transconductance 250 µmho 3
Error Amplifier Voltage Gain 500 V/V 3
VC Pin Source Current 15 µA VFB = 0.6V 3
VC Pin Sink Current 15 µA VFB = 1V 3
Switching Phase 180 Deg 3
Gate Rise Time 40 ns CLOAD = 3300pF 3
Gate Fall Time 60 ns CLOAD = 3300pF 3

CAD (KiCad official)

  • Symbol: LT3742EUF#PBF
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lt3742euf-pbf-etched.step / lt3742euf-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3742euf-pbf.step / lt3742euf-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (26 pp, sha256 65fb0720c261b313, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF