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LT3741EFE#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT3741EFE#TRPBF
Analog Devices · DC-DC Converters · TSSOP-20-EP
LT3741EFE#TRPBF from Analog Devices, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC_INT | power_out | A regulated 5V output that charges the CBOOT capacitor and powers the digital and switching subcircuits, current limited to 50mA, and it must be tied to the rail when VIN is below 6V. |
| 2 | GND | power_in | Ground pin for the controller, to be connected to the PCB ground together with the exposed pad. |
| 3 | VIN | power_in | Input supply pin for a 6V to 36V input range, which must be locally bypassed with a 4.7µF low-ESR capacitor to ground. |
| 4 | EN/UVLO | input | Enable pin that turns on the internal bias at a 1.55V falling threshold with 130mV hysteresis, has no internal pull-up or pull-down, and shuts down fully at about 0.5V. |
| 5 | VREF | power_out | Buffered 2V reference output capable of 0.5mA drive and current limited to 1mA. |
| 6 | CTRL2 | input | Thermal control input that reduces the regulated current level, with an analog control range of 0V to 1.5V. |
| 7 | GND | power_in | Ground pin for the controller. |
| 8 | CTRL1 | input | Analog input that sets the high-level regulated output current and overcurrent point, with its input internally clamped to 1.5V. |
| 9 | SS | passive | Soft-start pin that needs an external capacitor to ground, charged with an 11µA current source to limit regulated current during start-up. |
| 10 | FB | input | Feedback pin for voltage regulation with a 1.21V reference, where a feedback voltage above 1.5V triggers overvoltage protection that stops switching for 13µs. |
| 11 | SENSE+ | input | Connects to the external current sense resistor RS and is described as the inverting input of the average current mode loop error amplifier. |
| 12 | SENSE- | input | Connects to the output side of the sense resistor RS and is described as the non-inverting input of the average current mode loop error amplifier, with the reference current flowing out of this pin. |
| 13 | VC | passive | Compensation pin for the average current loop, with typical values of 20k to 50k for the resistor and 2nF to 5nF for the capacitor. |
| 14 | RT | passive | A resistor to ground sets the switching frequency from 200kHz to 1MHz, the pin is current limited to 60µA, and it must not be left open. |
| 15 | SYNC | input | Frequency synchronization input for an external clock, which should be grounded when not in use and requires the RT-set clock to run 20% slower than the SYNC frequency. |
| 16 | GND | power_in | Ground pin for the controller. |
| 17 | HG | output | High-side external power FET gate drive output with a 2.3Ω pull-up and 1.3Ω pull-down impedance. |
| 18 | SW | passive | Lower rail for the floating high-side driver that connects the two power FETs and the inductor. |
| 19 | CBOOT | power_out | Provides a floating 5V regulated supply for the high-side driver, charged through an external Schottky diode from VCC_INT. |
| 20 | LG | output | Low-side external power FET gate drive output with a 2.3Ω pull-up and 1.0Ω pull-down impedance. |
| 21 | GND | power_in | Exposed pad that is internally GND and must be soldered to the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | 6 | 36 | V | 3 | |||
| VIN Pin Quiescent Current, Non-Switching Operation | 1.8 | 2.5 | mA | Not Switching | 3 | ||
| VIN Pin Quiescent Current, Shutdown Mode | 0.1 | 1 | µA | VEN/UVLO = 0V, RT = 40kΩ | 3 | ||
| EN/UVLO Pin Falling Threshold | 1.49 | 1.55 | 1.61 | V | 3 | ||
| CTRL1 Pin Control Range | 0 | 1.5 | V | 3 | |||
| Reference Voltage (VREF Pin) | 1.94 | 2 | 2.06 | V | 3 | ||
| Full Range SENSE+ to SENSE- | 48 | 51 | 54 | mV | VCTRL1 = 1.5V | 3 | |
| Internal VCC Regulator Regulation Voltage (VCC_INT Pin) | 4.7 | 5 | 5.2 | V | 3 | ||
| Switching Frequency | fSW | 900 | 1000 | 1070 | kHz | RT = 40kΩ | 3 |
| Switching Frequency | fSW | 185 | 200 | 233 | kHz | RT = 200kΩ | 3 |
| Feedback Regulation Voltage | 1.192 | 1.21 | 1.228 | V | CTRL1 = 1.5V, ISENSE- = 23µA, VSENSE+ = 2V | 3 | |
| Current Control Loop gm Amp Offset Voltage | -3 | 0 | 3 | mV | VCM = 4V | 4 | |
| Current Control Loop gm | gm | 375 | 475 | 625 | µA/V | 4 | |
| VIN Voltage | 40 | V | 2 | ||||
| EN/UVLO Voltage | 6 | V | 2 | ||||
| VREF Voltage | 3 | V | 2 | ||||
| CTRL1 and CTRL2 Voltage | 3 | V | 2 | ||||
| SENSE+ Voltage | 40 | V | 2 | ||||
| SENSE- Voltage | 40 | V | 2 | ||||
| VC Voltage | 3 | V | 2 | ||||
| SW Voltage | 40 | V | 2 | ||||
| RT Voltage | 3 | V | 2 | ||||
| FB Voltage | 3 | V | 2 | ||||
| SS Voltage | 6 | V | 2 | ||||
| VCC_INT Voltage | 6 | V | 2 | ||||
| SYNC Voltage | 6 | V | 2 | ||||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Maximum Junction Temperature | TJMAX | 125 | °C | FE (TSSOP) package | 2 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 38 | °C/W | FE (TSSOP) package | 2 | ||
| Operating Junction Temperature Range | -40 | 125 | °C | LT3741E; specifications assured by design, characterization and SPC over this range (Note 2) | 4 | ||
| Guaranteed Junction Temperature Range for Performance Specifications | 0 | 125 | °C | LT3741E guaranteed to meet performance specifications (Note 2) | 4 |
CAD (KiCad official)
- Symbol:
LT3741EFE#TRPBF - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lt3741efe-trpbf-etched.step/lt3741efe-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3741efe-trpbf.step/lt3741efe-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
ffd25fe12b4612d5, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT3741EFE#TRPBF
**Analog Devices** · DC-DC Converters · TSSOP-20-EP
LT3741EFE#TRPBF from Analog Devices, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC_INT | power_out | A regulated 5V output that charges the CBOOT capacitor and powers the digital and switching subcircuits, current limited to 50mA, and it must be tied to the rail when VIN is below 6V. |
| 2 | GND | power_in | Ground pin for the controller, to be connected to the PCB ground together with the exposed pad. |
| 3 | VIN | power_in | Input supply pin for a 6V to 36V input range, which must be locally bypassed with a 4.7µF low-ESR capacitor to ground. |
| 4 | EN/UVLO | input | Enable pin that turns on the internal bias at a 1.55V falling threshold with 130mV hysteresis, has no internal pull-up or pull-down, and shuts down fully at about 0.5V. |
| 5 | VREF | power_out | Buffered 2V reference output capable of 0.5mA drive and current limited to 1mA. |
| 6 | CTRL2 | input | Thermal control input that reduces the regulated current level, with an analog control range of 0V to 1.5V. |
| 7 | GND | power_in | Ground pin for the controller. |
| 8 | CTRL1 | input | Analog input that sets the high-level regulated output current and overcurrent point, with its input internally clamped to 1.5V. |
| 9 | SS | passive | Soft-start pin that needs an external capacitor to ground, charged with an 11µA current source to limit regulated current during start-up. |
| 10 | FB | input | Feedback pin for voltage regulation with a 1.21V reference, where a feedback voltage above 1.5V triggers overvoltage protection that stops switching for 13µs. |
| 11 | SENSE+ | input | Connects to the external current sense resistor RS and is described as the inverting input of the average current mode loop error amplifier. |
| 12 | SENSE- | input | Connects to the output side of the sense resistor RS and is described as the non-inverting input of the average current mode loop error amplifier, with the reference current flowing out of this pin. |
| 13 | VC | passive | Compensation pin for the average current loop, with typical values of 20k to 50k for the resistor and 2nF to 5nF for the capacitor. |
| 14 | RT | passive | A resistor to ground sets the switching frequency from 200kHz to 1MHz, the pin is current limited to 60µA, and it must not be left open. |
| 15 | SYNC | input | Frequency synchronization input for an external clock, which should be grounded when not in use and requires the RT-set clock to run 20% slower than the SYNC frequency. |
| 16 | GND | power_in | Ground pin for the controller. |
| 17 | HG | output | High-side external power FET gate drive output with a 2.3Ω pull-up and 1.3Ω pull-down impedance. |
| 18 | SW | passive | Lower rail for the floating high-side driver that connects the two power FETs and the inductor. |
| 19 | CBOOT | power_out | Provides a floating 5V regulated supply for the high-side driver, charged through an external Schottky diode from VCC_INT. |
| 20 | LG | output | Low-side external power FET gate drive output with a 2.3Ω pull-up and 1.0Ω pull-down impedance. |
| 21 | GND | power_in | Exposed pad that is internally GND and must be soldered to the PCB. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | | 6 | | 36 | V | | 3 |
| VIN Pin Quiescent Current, Non-Switching Operation | | | 1.8 | 2.5 | mA | Not Switching | 3 |
| VIN Pin Quiescent Current, Shutdown Mode | | | 0.1 | 1 | µA | VEN/UVLO = 0V, RT = 40kΩ | 3 |
| EN/UVLO Pin Falling Threshold | | 1.49 | 1.55 | 1.61 | V | | 3 |
| CTRL1 Pin Control Range | | 0 | | 1.5 | V | | 3 |
| Reference Voltage (VREF Pin) | | 1.94 | 2 | 2.06 | V | | 3 |
| Full Range SENSE+ to SENSE- | | 48 | 51 | 54 | mV | VCTRL1 = 1.5V | 3 |
| Internal VCC Regulator Regulation Voltage (VCC_INT Pin) | | 4.7 | 5 | 5.2 | V | | 3 |
| Switching Frequency | fSW | 900 | 1000 | 1070 | kHz | RT = 40kΩ | 3 |
| Switching Frequency | fSW | 185 | 200 | 233 | kHz | RT = 200kΩ | 3 |
| Feedback Regulation Voltage | | 1.192 | 1.21 | 1.228 | V | CTRL1 = 1.5V, ISENSE- = 23µA, VSENSE+ = 2V | 3 |
| Current Control Loop gm Amp Offset Voltage | | -3 | 0 | 3 | mV | VCM = 4V | 4 |
| Current Control Loop gm | gm | 375 | 475 | 625 | µA/V | | 4 |
| VIN Voltage | | | | 40 | V | | 2 |
| EN/UVLO Voltage | | | | 6 | V | | 2 |
| VREF Voltage | | | | 3 | V | | 2 |
| CTRL1 and CTRL2 Voltage | | | | 3 | V | | 2 |
| SENSE+ Voltage | | | | 40 | V | | 2 |
| SENSE- Voltage | | | | 40 | V | | 2 |
| VC Voltage | | | | 3 | V | | 2 |
| SW Voltage | | | | 40 | V | | 2 |
| RT Voltage | | | | 3 | V | | 2 |
| FB Voltage | | | | 3 | V | | 2 |
| SS Voltage | | | | 6 | V | | 2 |
| VCC_INT Voltage | | | | 6 | V | | 2 |
| SYNC Voltage | | | | 6 | V | | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Maximum Junction Temperature | TJMAX | | | 125 | °C | FE (TSSOP) package | 2 |
| Junction-to-Ambient Thermal Resistance | θJA | | 38 | | °C/W | FE (TSSOP) package | 2 |
| Operating Junction Temperature Range | | -40 | | 125 | °C | LT3741E; specifications assured by design, characterization and SPC over this range (Note 2) | 4 |
| Guaranteed Junction Temperature Range for Performance Specifications | | 0 | | 125 | °C | LT3741E guaranteed to meet performance specifications (Note 2) | 4 |
## CAD (KiCad official)
- Symbol: `LT3741EFE#TRPBF`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `lt3741efe-trpbf-etched.step` / `lt3741efe-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt3741efe-trpbf.step` / `lt3741efe-trpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588905055219568640) (24 pp, sha256 `ffd25fe12b4612d5`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt3741efe-trpbf-datasheet.pdf)