component
LT3724EFE#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLT3724EFE#TRPBF
Analog Devices · DC-DC Converters · TSSOP-16-EP
LT3724EFE#TRPBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | The VIN pin is the main supply pin and should be decoupled to SGND with a low ESR capacitor located close to the pin, with an operating input range of 4V to 60V. |
| 2 | NC | unconnected | No Connection. |
| 3 | SHDN | input | The SHDN pin has a precision enable threshold of 1.35V (rising) with 120mV of hysteresis for UVLO implementation, and pulling it below a VBE (0.7V) puts the part into a low current shutdown mode with VIN supply current reduced to approximately 10µA. |
| 4 | CSS | passive | The soft-start pin is connected to VOUT via a ceramic capacitor and 200kΩ series resistor, controlling output slew to a 2µA average current through the soft-start capacitor, and shorting it to SGND disables soft-start. |
| 5 | BURST_EN | input | The BURST_EN pin enables Burst Mode operation when connected to ground and disables it when connected to VCC. |
| 6 | VFB | input | The VFB pin is the output voltage feedback input, externally connected to the supply output through a resistive divider, and regulates to 1.231V at the inverting input of the error amplifier. |
| 7 | VC | passive | The VC pin is the error amplifier output that sets peak switch current and is normally compensated with an RC network to SGND, and it cannot be pulled low with a low impedance source (drive it only through a 1kΩ series resistance if externally manipulated). |
| 8 | SGND | power_in | The SGND pin is the low noise ground reference and should be connected to the -VOUT side of the output capacitors, with high currents kept away from this connection. |
| 9 | SENSE- | input | The SENSE- pin is the negative input of the current sense amplifier, connected to the VOUT side of the sense resistor in step-down applications, with the inductor current limit set to 150mV across the SENSE inputs. |
| 10 | SENSE+ | input | The SENSE+ pin is the positive input of the current sense amplifier, connected to the inductor side of the sense resistor in step-down applications, with the current limit set to 150mV across the SENSE inputs. |
| 11 | PGND | power_in | The PGND pin is the high-current ground reference for the internal low side switch and VCC regulator and should connect directly to the negative terminal of the VCC decoupling capacitor. |
| 12 | VCC | power_out | The VCC pin is the internal bias supply node decoupled with a low ESR 1µF ceramic capacitor to PGND, regulated to 8.3V typical and able to be back driven from an external supply to improve efficiency. |
| 13 | NC | unconnected | No Connection. |
| 14 | SW | passive | The SW pin connects to the external Schottky clamp diode cathode, the power MOSFET source and the inductor, swinging from VIN during the on-time to a Schottky drop below ground during the off-time. |
| 15 | TG | output | The TG pin is the bootstrapped gate drive for the top N-channel MOSFET and should be connected to the MOSFET gate with a short, wide PCB trace to minimize inductance. |
| 16 | BOOST | passive | The BOOST pin supplies the bootstrapped gate drive and connects to a low ESR ceramic boost capacitor referenced to SW, with a maximum voltage of VIN + VCC ground referred. |
| 17 | SGND | power_in | The exposed pad is internally connected to the SGND pin and must be soldered to the PCB ground for electrical contact and optimal thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Voltage Range | VIN | 4 | V | 2 | |||
| Minimum Start Voltage | 7.5 | V | 2 | ||||
| UVLO Threshold (Falling) | 3.65 | 3.8 | 3.95 | V | 2 | ||
| VIN Supply Current | IVIN | 20 | µA | VCC > 9V | 2 | ||
| VIN Burst Mode Current | 20 | µA | VBURST_EN = 0V, VFB = 1.35V | 2 | |||
| VIN Shutdown Current | 10 | 15 | µA | VSHDN = 0V | 2 | ||
| BOOST Supply Current | IBOOST | 1.4 | mA | 3 | |||
| BOOST Burst Mode Current | 0.1 | µA | VBURST_EN = 0V | 3 | |||
| BOOST Shutdown Current | 0.1 | µA | VSHDN = 0V | 3 | |||
| VFB Error Amp Reference Voltage | VFB | 1.224 | 1.231 | 1.238 | V | Measured at VFB pin | 3 |
| Feedback Input Current | IFB | 25 | nA | 3 | |||
| SHDN Enable Threshold (Rising) | VSHDN | 1.3 | 1.35 | 1.4 | V | 3 | |
| SHDN Threshold Hysteresis | 120 | mV | 3 | ||||
| VSENSE Common Mode Range | VSENSE | 0 | 36 | V | 3 | ||
| Current Limit Sense Voltage | VSENSE+, VSENSE- | 140 | 150 | 175 | mV | 3 | |
| Soft-Start Disable Voltage | VFB(SS) | 1.185 | V | VFB rising | 3 | ||
| Soft-Start Disable Hysteresis | 300 | mV | 3 | ||||
| Soft-Start Capacitor Control Current | ISS | 2 | µA | 3 | |||
| Error Amp Transconductance | gm | 275 | 340 | 400 | µmhos | 3 | |
| Error Amp Sink/Source Current | IVC | -30 | 30 | µA | 3 | ||
| Operating Junction Temperature Range (LT3724E) | TJ | -40 | 125 | °C | LT3724E | 2 | |
| Input Supply Voltage (VIN) | VIN | -0.3 | 65 | V | 2 | ||
| Boosted Supply Voltage (BOOST) | BOOST | -0.3 | 80 | V | 2 | ||
| Switch Voltage (SW) | SW | -1 | 65 | V | 2 | ||
| Differential Boost Voltage (BOOST to SW) | -0.3 | 24 | V | 2 | |||
| Bias Supply Voltage (VCC) | VCC | -0.3 | 24 | V | 2 | ||
| SENSE+ and SENSE- Voltages | SENSE+, SENSE- | -0.3 | 40 | V | 2 | ||
| SENSE+ to SENSE- Differential Voltage | -1 | 1 | V | 2 | |||
| BURST_EN Voltage | BURST_EN | -0.3 | 24 | V | 2 | ||
| VC, VFB, CSS, and SHDN Voltages | VC, VFB, CSS, SHDN | -0.3 | 5 | V | 2 | ||
| CSS and SHDN Pin Currents | 1 | mA | 2 | ||||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Lead Temperature (Soldering) | 300 | °C | 10 sec | 2 | |||
| Maximum Junction Temperature | TJMAX | 125 | °C | 2 | |||
| Junction-to-Ambient Thermal Resistance | θJA | 40 | °C/W | 2 | |||
| Junction-to-Case Thermal Resistance | θJC | 10 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
LT3724EFE#TRPBF - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lt3724efe-trpbf-etched.step/lt3724efe-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3724efe-trpbf.step/lt3724efe-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
e8d21eb29decddb8, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).