component
LT3580EMS8E#TRPBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, MSOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT3580EMS8E#TRPBF
Analog Devices · DC-DC Converters · MSOP-8-EP
LT3580EMS8E#TRPBF from Analog Devices, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Positive and negative feedback pin; the feedback resistor from VOUT to FB sets the output, using the 1.215V reference for boost/SEPIC and 5mV for inverting configurations, with an absolute maximum of -0.3V to 2.5V. |
| 2 | VC | passive | Error amplifier output pin to which the external compensation network is tied, with an absolute maximum range of -0.3V to 2V. |
| 3 | VIN | power_in | Input supply pin that must be locally bypassed; operating range is 2.5V to 32V with an absolute maximum of -0.3V to 32V. |
| 4 | SW | output | Switch pin, the collector of the internal NPN power switch; minimize the metal trace area connected to it to minimize EMI, with an absolute maximum of -0.4V to 42V. |
| 5 | SHDN | input | Shutdown pin with UVLO function that must not float: drive below 1.24V (LT3580E, LT3580I) or 1.22V (LT3580H, LT3580MP) to disable the chip, and above 1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP) to enable it and restart soft-start; absolute maximum is 32V. |
| 6 | RT | passive | Timing resistor pin; a resistor from this pin to ground sets the fixed free-running switching frequency, the pin must not float, and its absolute maximum is 5V. |
| 7 | SS | passive | Soft-start pin where the soft-start capacitor is placed; it is charged through a nominal 275k resistor to about 2.2V, with an absolute maximum of 2.5V. |
| 8 | SYNC | input | Synchronization input for an external clock, where the high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts to the internal free-running clock, with an absolute maximum of 5.5V. |
| 9 | GND | power_in | Ground on the exposed pad, which must be soldered directly to the local ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage Range | 2.5 | 32 | V | 3 | |||
| Positive Feedback Voltage | 1.195 | 1.215 | 1.23 | V | 3 | ||
| Negative Feedback Voltage | 0 | 5 | 12 | mV | 3 | ||
| Positive FB Pin Bias Current | 81 | 83.3 | 85 | μA | VFB = Positive Feedback Voltage, Current Into Pin | 3 | |
| Negative FB Pin Bias Current (LT3580E) | 81 | 83.3 | 85.5 | μA | VFB = Negative Feedback Voltage, Current Out of Pin | 3 | |
| Quiescent Current | 1 | 1.5 | mA | VSHDN = 2.5V, Not Switching | 3 | ||
| Quiescent Current in Shutdown | 0 | 1 | μA | VSHDN = 0V | 3 | ||
| Reference Line Regulation | 0.01 | 0.05 | %/V | 2.5V ≤ VIN ≤ 32V | 3 | ||
| Switching Frequency fOSC (E grade) | fOSC | 1.8 | 2 | 2.2 | MHz | RT = 45.3k | 3 |
| Switching Frequency fOSC (E grade) | fOSC | 180 | 200 | 220 | kHz | RT = 464k | 3 |
| Switching Frequency Set Range | 200 | 2500 | kHz | SYNCing or Free Running | 3 | ||
| SYNC High Level for Synchronization | 1.3 | V | 3 | ||||
| SYNC Low Level for Synchronization | 0.4 | V | 3 | ||||
| SYNC Clock Pulse Duty Cycle | 35 | 65 | % | VSYNC = 0V to 2V | 3 | ||
| Switch Current Limit, Minimum Duty Cycle (E grade) | 2.2 | 2.5 | 2.8 | A | Minimum Duty Cycle (Note 3) | 3 | |
| Switch Current Limit, Maximum Duty Cycle (E grade) | 1.6 | 1.9 | 2.6 | A | Maximum Duty Cycle (Notes 3, 4) | 3 | |
| Soft-Start Charging Current | 4 | 6 | 8 | μA | VSS = 0.5V | 3 | |
| SHDN Minimum Input Voltage High, Rising (E grade) | 1.27 | 1.32 | 1.38 | V | Active Mode, SHDN Rising | 3 | |
| SHDN Minimum Input Voltage High, Falling (E grade) | 1.24 | 1.29 | 1.33 | V | Active Mode, SHDN Falling | 3 | |
| SHDN Input Voltage Low | 0.3 | V | Shutdown Mode | 3 | |||
| SHDN Pin Bias Current | 9.7 | 11.6 | 13.4 | μA | VSHDN = 3V | 3 | |
| SHDN Pin Bias Current | 40 | 60 | μA | VSHDN = 1.3V | 3 | ||
| SHDN Pin Bias Current | 0 | 0.1 | μA | VSHDN = 0V | 3 | ||
| Switch Leakage Current | 0.01 | 1 | μA | VSW = 5V | 3 | ||
| VIN Voltage (absolute maximum) | -0.3 | 32 | V | 2 | |||
| SW Voltage (absolute maximum) | -0.4 | 42 | V | 2 | |||
| RT Voltage (absolute maximum) | -0.3 | 5 | V | 2 | |||
| SS and FB Voltage (absolute maximum) | -0.3 | 2.5 | V | 2 | |||
| VC Voltage (absolute maximum) | -0.3 | 2 | V | 2 | |||
| SHDN Voltage (absolute maximum) | -0.3 | 32 | V | 2 | |||
| SYNC Voltage (absolute maximum) | -0.3 | 5.5 | V | 2 | |||
| Operating Junction Temperature Range (LT3580E) | TJ | -40 | 125 | °C | Notes 2, 5 | 2 | |
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Thermal Resistance Junction-to-Ambient (MS8E MSOP, exposed pad) | θJA | 35 | 40 | °C/W | 8-lead MSOP exposed pad package, printed as 35°C/W to 40°C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | into the system ground plane at the C3 ground terminal. The cut ground copper at D1’s cathode is essential to | 16 |
CAD (KiCad official)
- Symbol:
LT3580EMS8E#TRPBF - Footprint:
Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm - 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
lt3580ems8e-trpbf-etched.step/lt3580ems8e-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3580ems8e-trpbf.step/lt3580ems8e-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
f12b3fa212ceb5f3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT3580EMS8E#TRPBF
**Analog Devices** · DC-DC Converters · MSOP-8-EP
LT3580EMS8E#TRPBF from Analog Devices, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Positive and negative feedback pin; the feedback resistor from VOUT to FB sets the output, using the 1.215V reference for boost/SEPIC and 5mV for inverting configurations, with an absolute maximum of -0.3V to 2.5V. |
| 2 | VC | passive | Error amplifier output pin to which the external compensation network is tied, with an absolute maximum range of -0.3V to 2V. |
| 3 | VIN | power_in | Input supply pin that must be locally bypassed; operating range is 2.5V to 32V with an absolute maximum of -0.3V to 32V. |
| 4 | SW | output | Switch pin, the collector of the internal NPN power switch; minimize the metal trace area connected to it to minimize EMI, with an absolute maximum of -0.4V to 42V. |
| 5 | SHDN | input | Shutdown pin with UVLO function that must not float: drive below 1.24V (LT3580E, LT3580I) or 1.22V (LT3580H, LT3580MP) to disable the chip, and above 1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP) to enable it and restart soft-start; absolute maximum is 32V. |
| 6 | RT | passive | Timing resistor pin; a resistor from this pin to ground sets the fixed free-running switching frequency, the pin must not float, and its absolute maximum is 5V. |
| 7 | SS | passive | Soft-start pin where the soft-start capacitor is placed; it is charged through a nominal 275k resistor to about 2.2V, with an absolute maximum of 2.5V. |
| 8 | SYNC | input | Synchronization input for an external clock, where the high level must exceed 1.3V and the low level must be below 0.4V; driving it below 0.4V reverts to the internal free-running clock, with an absolute maximum of 5.5V. |
| 9 | GND | power_in | Ground on the exposed pad, which must be soldered directly to the local ground plane. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage Range | | 2.5 | | 32 | V | | 3 |
| Positive Feedback Voltage | | 1.195 | 1.215 | 1.23 | V | | 3 |
| Negative Feedback Voltage | | 0 | 5 | 12 | mV | | 3 |
| Positive FB Pin Bias Current | | 81 | 83.3 | 85 | μA | VFB = Positive Feedback Voltage, Current Into Pin | 3 |
| Negative FB Pin Bias Current (LT3580E) | | 81 | 83.3 | 85.5 | μA | VFB = Negative Feedback Voltage, Current Out of Pin | 3 |
| Quiescent Current | | | 1 | 1.5 | mA | VSHDN = 2.5V, Not Switching | 3 |
| Quiescent Current in Shutdown | | 0 | | 1 | μA | VSHDN = 0V | 3 |
| Reference Line Regulation | | | 0.01 | 0.05 | %/V | 2.5V ≤ VIN ≤ 32V | 3 |
| Switching Frequency fOSC (E grade) | fOSC | 1.8 | 2 | 2.2 | MHz | RT = 45.3k | 3 |
| Switching Frequency fOSC (E grade) | fOSC | 180 | 200 | 220 | kHz | RT = 464k | 3 |
| Switching Frequency Set Range | | 200 | | 2500 | kHz | SYNCing or Free Running | 3 |
| SYNC High Level for Synchronization | | 1.3 | | | V | | 3 |
| SYNC Low Level for Synchronization | | | | 0.4 | V | | 3 |
| SYNC Clock Pulse Duty Cycle | | 35 | | 65 | % | VSYNC = 0V to 2V | 3 |
| Switch Current Limit, Minimum Duty Cycle (E grade) | | 2.2 | 2.5 | 2.8 | A | Minimum Duty Cycle (Note 3) | 3 |
| Switch Current Limit, Maximum Duty Cycle (E grade) | | 1.6 | 1.9 | 2.6 | A | Maximum Duty Cycle (Notes 3, 4) | 3 |
| Soft-Start Charging Current | | 4 | 6 | 8 | μA | VSS = 0.5V | 3 |
| SHDN Minimum Input Voltage High, Rising (E grade) | | 1.27 | 1.32 | 1.38 | V | Active Mode, SHDN Rising | 3 |
| SHDN Minimum Input Voltage High, Falling (E grade) | | 1.24 | 1.29 | 1.33 | V | Active Mode, SHDN Falling | 3 |
| SHDN Input Voltage Low | | | | 0.3 | V | Shutdown Mode | 3 |
| SHDN Pin Bias Current | | 9.7 | 11.6 | 13.4 | μA | VSHDN = 3V | 3 |
| SHDN Pin Bias Current | | 40 | | 60 | μA | VSHDN = 1.3V | 3 |
| SHDN Pin Bias Current | | 0 | | 0.1 | μA | VSHDN = 0V | 3 |
| Switch Leakage Current | | | 0.01 | 1 | μA | VSW = 5V | 3 |
| VIN Voltage (absolute maximum) | | -0.3 | | 32 | V | | 2 |
| SW Voltage (absolute maximum) | | -0.4 | | 42 | V | | 2 |
| RT Voltage (absolute maximum) | | -0.3 | | 5 | V | | 2 |
| SS and FB Voltage (absolute maximum) | | -0.3 | | 2.5 | V | | 2 |
| VC Voltage (absolute maximum) | | -0.3 | | 2 | V | | 2 |
| SHDN Voltage (absolute maximum) | | -0.3 | | 32 | V | | 2 |
| SYNC Voltage (absolute maximum) | | -0.3 | | 5.5 | V | | 2 |
| Operating Junction Temperature Range (LT3580E) | TJ | -40 | | 125 | °C | Notes 2, 5 | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Thermal Resistance Junction-to-Ambient (MS8E MSOP, exposed pad) | θJA | 35 | | 40 | °C/W | 8-lead MSOP exposed pad package, printed as 35°C/W to 40°C/W | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | into the system ground plane at the C3 ground terminal. The cut ground copper at D1’s cathode is essential to | 16 |
## CAD (KiCad official)
- Symbol: `LT3580EMS8E#TRPBF`
- Footprint: `Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm`
- 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `lt3580ems8e-trpbf-etched.step` / `lt3580ems8e-trpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt3580ems8e-trpbf.step` / `lt3580ems8e-trpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906305629536256) (28 pp, sha256 `f12b3fa212ceb5f3`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt3580ems8e-trpbf-datasheet.pdf)