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LT3430EFE#TRPBF

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Analog Devices DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT3430EFE#TRPBF

Analog Devices · DC-DC Converters · TSSOP-16-EP

LT3430EFE#TRPBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Reference ground for the regulated output; keep the paths to load ground short, since load regulation suffers if the load ground is not at the GND pin voltage.
2 SW output Emitter of the on-chip NPN power switch, driven up to the input pin voltage during switch on-time, with negative switch voltage clamped by the external catch diode to a maximum of -0.8V.
3 VIN power_in Collector of the on-chip NPN power switch that also powers the internal control circuitry when no voltage is present on the BIAS pin; keep the path from VIN through the input capacitor and catch diode short.
4 VIN power_in Collector of the on-chip NPN power switch that also powers the internal control circuitry when no voltage is present on the BIAS pin; pins 3 and 4 are shorted together on the PCB.
5 SW output Emitter of the on-chip NPN power switch, driven up to the input pin voltage during switch on-time, with negative switch voltage clamped by the external catch diode to a maximum of -0.8V.
6 BOOST power_in Supplies a drive voltage higher than VIN to the internal NPN switch so it saturates; the boost capacitor and diode generate this voltage externally (absolute maximum BOOST pin voltage 68V, BOOST above SW 35V).
7 NC unconnected No connection.
8 GND power_in Reference ground for the regulated output; solder to a continuous copper ground plane under the die for thermal and electrical performance.
9 GND power_in Reference ground for the regulated output; solder to a continuous copper ground plane under the die for thermal and electrical performance.
10 BIAS power_in Connect to the regulated output (minimum output setting of 3V for this mode) so internal circuitry draws operating current from the output instead of VIN to improve efficiency.
11 VC passive Error amplifier output and peak switch current comparator input used for compensation; it sits near 0.9V at light load and 2.1V at maximum load, can be driven to ground to shut off the regulator, and must be current-limited to 4mA if driven high.
12 FB input Feedback input that regulates to 1.22V through an external divider; below 0.6V it reduces switch current limit and disables SYNC, and below 0.8V it reduces switching frequency.
13 NC unconnected No connection.
14 SYNC input Logic-compatible input that synchronizes the internal oscillator, accepting 10% to 90% duty cycle signals in the range 228kHz to 700kHz for the LT3430 or 125kHz to 250kHz for the LT3430-1.
15 SHDN input Shutdown input with a 2.38V threshold that disables switching (acting as accurate UVLO) and a 0.4V threshold that forces micropower shutdown; it may be left open or forced high to no more than 6V.
16 GND power_in Reference ground for the regulated output; solder to the continuous copper ground plane under the die to reduce thermal resistance.
17 GND power_in Exposed pad fused to the GND pins that must be soldered to the copper ground plane under the device to reduce thermal resistance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16-EP
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference Voltage (VREF), 25°C row VREF 1.204 1.219 1.234 V VOL + 0.2 ≤ VC ≤ VOH, 0.2; 5.5V ≤ VIN ≤ 60V 2
Reference Voltage, full temperature range VREF 1.195 1.219 1.243 V ● full operating temperature range; VOL + 0.2 ≤ VC ≤ VOH, 0.2; 5.5V ≤ VIN ≤ 60V 2
Error Amp gm, 25°C row gm 1650 2200 3300 µMho dl (VC) = ±10µA 2
Error Amp gm, full temperature range gm 1000 2200 4200 µMho ● dl (VC) = ±10µA 2
EA Source Current 125 225 450 µA FB = 1V ● 2
EA Sink Current 100 225 500 µA FB = 1.4V ● 2
Switch Current Limit, cold to 25°C 3 5 6.5 A VC Open, Boost = VIN + 5V, FB = 1V; -40°C ≤ TJ ≤ 25°C 2
Switch Current Limit, TJ = 125°C 2.5 4 5.5 A VC Open, Boost = VIN + 5V, FB = 1V; TJ = 125°C (Note 9) 2
Maximum Switch Duty Cycle (LT3430), row 1 93 96 % FB = 1V ● 2
Maximum Switch Duty Cycle (LT3430), row 2 90 % FB = 1V ● 2
Switch Frequency (LT3430), row 1 fSW 184 200 216 kHz VC Set to Give DC = 50% ● 3
Switch Frequency (LT3430), row 2 fSW 172 200 228 kHz VC Set to Give DC = 50% ● 3
Boost Current, ISW = 0.75A 25 50 mA Boost = VIN + 5V, ISW = 0.75A ● 3
Boost Current, ISW = 2.5A 75 120 mA Boost = VIN + 5V, ISW = 2.5A ● 3
Shutdown Supply Current, row 1 30 100 µA SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open ● 3
Shutdown Supply Current, row 2 200 µA SHDN = 0V, VIN ≤ 60V, SW = 0V, VC Open ● 3
Minimum Input Voltage 4.6 5.5 V Note 3 ● 3
Minimum Boost Voltage 1.8 3 V ISW ≤ 2.5A ● 3
FB Input Bias Current -0.2 -1.5 µA ● 2
Error Amp Voltage Gain 200 400 V/V Note 2 2
Switch On Resistance, row 1 0.1 0.14 Ω ISW = 2.5A, Boost = VIN + 5V (Note 7) 2
Switch On Resistance, row 2 0.18 Ω ISW = 2.5A, Boost = VIN + 5V (Note 7) 2
Input Supply Current (IVIN) IVIN 1.5 2.2 mA VBIAS = 5V (Note 6) 3
Bias Supply Current (IBIAS) IBIAS 3.1 4.2 mA VBIAS = 5V (Note 6) 3
Line Regulation of fSW fSW 0.05 0.15 %/V 5.5V ≤ VIN ≤ 60V ● 3
Lockout Threshold 2.3 2.42 2.53 V VC Open ● 3
Shutdown Threshold, shutting down 0.15 0.37 0.58 V VC Open, Shutting Down ● 3
Shutdown Threshold, starting up 0.25 0.42 0.6 V VC Open, Starting Up ● 3
SYNC Frequency Range (LT3430) 228 700 kHz 3
Input Voltage (VIN) VIN 60 V 2
BOOST Pin Above SW 35 V Note 11 2
BOOST Pin Voltage 68 V 2
SYNC Voltage 7 V 2
SHDN Voltage SHDN 6 V 2
BIAS Pin Voltage 30 V 2
FB Pin Voltage 3.5 V 2
FB Pin Current 2 mA 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (Soldering, 10 sec) 300 °C 10 sec 2
Operating Junction Temperature Range (LT3430EFE) TJ -40 125 °C Notes 8, 10 2
Maximum Junction Temperature TJMAX 125 °C 2
Junction-to-Ambient Thermal Resistance θJA 45 °C/W 2
Junction-to-Case Thermal Resistance θJC 10 °C/W 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper exposed pad that is fused to the GND pins. The pad (Pin 17) should be soldered to the copper ground plane under 6

CAD (KiCad official)

  • Symbol: LT3430EFE#TRPBF
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lt3430efe-trpbf-etched.step / lt3430efe-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3430efe-trpbf.step / lt3430efe-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 9f1cac6b1eef7576, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF