component
LT3154AV#PBF
Public Made by Adomby adom
Analog Devices DC-DC Converters, LQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LT3154AV#PBF
Analog Devices · DC-DC Converters · LQFN-16(3x3)
LT3154AV#PBF from Analog Devices, in a LQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PVIN | power_in | Power input for the buck-boost converter; connect a minimum 22µF low ESR capacitor to PGND as close to the device as possible, and connect it to VIN in the application. |
| 2 | PVIN | power_in | Power input for the buck-boost converter; connect a minimum 22µF low ESR capacitor to PGND as close to the device as possible, and connect it to VIN in the application. |
| 3 | VIN | power_in | Signal input voltage with an operating range of 1.8V to 5.5V; decouple with a minimum 1µF capacitor and provide a low-noise input for the control circuitry. |
| 4 | EN/UVLO | input | Enable and programmable UVLO input; connect to VIN for 1.8V minimum operation or to a resistor divider, with a 1.2V rising and 1.1V falling threshold and 100mV internal hysteresis, and it must be below 0.3V for full shutdown. |
| 5 | SYNC/MODE | input | Selects Burst Mode operation (low), PWM operation with Burst Mode disabled (high, VIN), or synchronization to an external clock with a pulse width between 75ns and T period minus 75ns; this pin must not be left floating. |
| 6 | RT | input | Oscillator frequency programming input; connect to VIN for 2.2MHz fixed frequency, or connect a resistor to GND per RT(kΩ) = 110 / fSW(MHz) for frequencies from 400kHz to 4MHz. |
| 7 | GND | power_in | Signal ground providing a low-noise ground for the control circuits; it must be connected to PGND in the application. |
| 8 | SS | input | External soft-start input; connect to VIN for the default 2.2ms soft-start period, or connect a capacitor to GND with tSS(ms) = 0.8 × CSS(nF). |
| 9 | FB | input | Feedback input to the error amplifier, where the resistor divider sets VOUT = 0.99V × (1 + R3/R4) and the feedback voltage is 0.98V to 1.02V. |
| 10 | VC | passive | Voltage error amplifier output used to command average inductor current, with an R-C network to ground setting the voltage loop compensation; its full-scale range is 200mV to 900mV. |
| 11 | VOUT | input | Output voltage sense and low-noise control input; decouple with a minimum 1µF capacitor, and it must be connected to PVOUT in the application. |
| 12 | PVOUT | power_out | Power output for the buck-boost converter; connect a minimum 68µF low ESR capacitor to PGND as close to the device as possible, and connect it to VOUT in the application. |
| 13 | SW2 | output | Buck-boost converter switch pin; connect the inductor between SW1 and SW2. |
| 14 | PGND | power_in | Power ground connection that must make full connection to the PCB ground plane to meet the specified thermal requirements, and it must be connected to GND in the application. |
| 15 | PGND | power_in | Power ground connection that must make full connection to the PCB ground plane to meet the specified thermal requirements, and it must be connected to GND in the application. |
| 16 | SW1 | output | Buck-boost converter switch pin; connect the inductor between SW1 and SW2. |
| 17 | PGND | power_in | Exposed thermal pad that is the power ground connection and must be soldered to the PCB ground plane to meet the specified thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Voltage | 1.8 | 5.5 | V | EN/UVLO > 1.24V | 3 | ||
| VOUT Operating Voltage | 1.8 | 5.5 | V | Adjustable Version with External Divider | 3 | ||
| Feedback Voltage | 0.98 | 1 | 1.02 | V | 3 | ||
| Sleep Quiescent Current, VIN | 15 | 25 | µA | SYNC/MODE = 0V, VOUT in Regulation, Non-Switching | 3 | ||
| Sleep Quiescent Current, VOUT | 1 | 2 | µA | SYNC/MODE = 0V | 3 | ||
| Shutdown Current, VIN | 0.5 | 2 | µA | EN/UVLO = 0V, SS = 0V (Note 7) | 3 | ||
| Current in UVLO, VIN | 8 | 25 | µA | EN/UVLO = 1.05V | 3 | ||
| EN/UVLO Pin Rising Threshold | 1.16 | 1.2 | 1.24 | V | 3 | ||
| EN/UVLO Pin Falling Threshold | 1.06 | 1.1 | 1.14 | V | 3 | ||
| EN/UVLO Pin Input Leakage Current | 1 | 50 | nA | EN/UVLO = 5V | 3 | ||
| EN/UVLO Pin Shutdown Threshold | 0.2 | 0.75 | 1.05 | V | EN/UVLO Pin Voltage | 3 | |
| Average Inductor Current Limit | 5.5 | 6.5 | 8.7 | A | 3 | ||
| Peak Inductor Current Limit | 8 | 9.5 | 11 | A | 3 | ||
| IZERO Current | -0.25 | 0 | 0.25 | A | SYNC/MODE = 0V | 3 | |
| Reverse Inductor Current Limit | -1.5 | -1.2 | -0.9 | A | SYNC/MODE = 3.6V | 3 | |
| Lowside MOSFETs Leakage Currents | 0.05 | 2 | µA | VSW = 5.5V, EN/UVLO = 0 | 3 | ||
| Highside MOSFETs Leakage Current | 0.1 | 10 | µA | VIN = VOUT = 5.5V, VSW1 = VSW2 = 0V, EN/UVLO = 0 | 3 | ||
| Switching Frequency | 1.8 | 2.2 | 2.6 | MHz | RT to VIN or RT = 49.9kΩ | 3 | |
| Switching Frequency Range | 0.4 | 4 | MHz | RT Programmable | 3 | ||
| Max Boost Duty Cycle (SW2 Low) | 83 | 88 | 93 | % | RT = VIN, FB or VOUT 5% Below Regulation Value | 3 | |
| SYNC/MODE Applied Clock Frequency | 0.5 | 4 | MHz | RT Chosen to Program a 25% Lower Frequency | 3 | ||
| SYNC/MODE Input High Logic Level | 1.5 | V | 3 | ||||
| SYNC/MODE Input Low Logic Level | 0.5 | V | 3 | ||||
| SYNC/MODE Input Leakage Current | 1 | 50 | nA | SYNC/MODE = 5V | 3 | ||
| Feedback Pin Input Current | 0 | 50 | nA | FB = 1V | 3 | ||
| VC Source/Sink Current | -12 | 12 | µA | FB = 0.9V Source, FB = 1.1V Sink | 3 | ||
| PWM Mode No-Load Current, VIN | 20 | mA | 3 | ||||
| Lowside (B & C) MOSFET RDS(ON) | 18 | mΩ | VIN = 3.6V, VOUT = 3.0V | 3 | |||
| Highside (A & D) MOSFET RDS(ON) | 25 | mΩ | VIN = VOUT = 3.6V | 3 | |||
| Min Duty Cycle (SW1 High) | 0 | % | RT = VIN, FB or VOUT 5% Above Regulation Value | 3 | |||
| SYNC/MODE High or Low Pulse Width | 75 | ns | 3 | ||||
| Soft-Start Period (CSS Charge Time to 0.8V) | 2.2 | ms | SS = VIN or CSS = 2.7nF | 3 | |||
| External SS Regulation Voltage | 1 | V | Capacitor to GND Sets SS Time | 3 | |||
| Error Amplifier Transconductance | 110 | µS | VC Current = ±4µA | 3 | |||
| Supply Voltages (PVIN, VIN, PVOUT, VOUT) | -0.3 | 6 | V | 2 | |||
| SW1, SW2 Voltage DC | -0.3 | 6 | V | DC | 2 | ||
| SW1, SW2 Voltage Pulsed | -1 | 7 | V | PULSED (< 100ns) | 2 | ||
| All Other Pins Voltage | -0.3 | 6 | V | 2 | |||
| Operating Junction Temperature Range (LT3154E/LT3154I) | -40 | 125 | °C | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Maximum Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Thermal Resistance Junction-to-Ambient (demoboard) | θJA | 22 | °C/W | DEMOBOARD | 2 | ||
| Thermal Resistance Junction-to-Case | θJC | 9 | °C/W | 2 | |||
| Thermal Resistance Junction-to-Ambient (JEDEC) | θJA | 42 | °C/W | JEDEC (Note 5) | 2 |
CAD (KiCad official)
- Symbol:
LT3154AV#PBF - Footprint:
Package_DFN_QFN:LQFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
lt3154av-pbf-etched.step/lt3154av-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3154av-pbf.step/lt3154av-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
297cf4adc4d1d32a, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LT3154AV#PBF
**Analog Devices** · DC-DC Converters · LQFN-16(3x3)
LT3154AV#PBF from Analog Devices, in a LQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PVIN | power_in | Power input for the buck-boost converter; connect a minimum 22µF low ESR capacitor to PGND as close to the device as possible, and connect it to VIN in the application. |
| 2 | PVIN | power_in | Power input for the buck-boost converter; connect a minimum 22µF low ESR capacitor to PGND as close to the device as possible, and connect it to VIN in the application. |
| 3 | VIN | power_in | Signal input voltage with an operating range of 1.8V to 5.5V; decouple with a minimum 1µF capacitor and provide a low-noise input for the control circuitry. |
| 4 | EN/UVLO | input | Enable and programmable UVLO input; connect to VIN for 1.8V minimum operation or to a resistor divider, with a 1.2V rising and 1.1V falling threshold and 100mV internal hysteresis, and it must be below 0.3V for full shutdown. |
| 5 | SYNC/MODE | input | Selects Burst Mode operation (low), PWM operation with Burst Mode disabled (high, VIN), or synchronization to an external clock with a pulse width between 75ns and T period minus 75ns; this pin must not be left floating. |
| 6 | RT | input | Oscillator frequency programming input; connect to VIN for 2.2MHz fixed frequency, or connect a resistor to GND per RT(kΩ) = 110 / fSW(MHz) for frequencies from 400kHz to 4MHz. |
| 7 | GND | power_in | Signal ground providing a low-noise ground for the control circuits; it must be connected to PGND in the application. |
| 8 | SS | input | External soft-start input; connect to VIN for the default 2.2ms soft-start period, or connect a capacitor to GND with tSS(ms) = 0.8 × CSS(nF). |
| 9 | FB | input | Feedback input to the error amplifier, where the resistor divider sets VOUT = 0.99V × (1 + R3/R4) and the feedback voltage is 0.98V to 1.02V. |
| 10 | VC | passive | Voltage error amplifier output used to command average inductor current, with an R-C network to ground setting the voltage loop compensation; its full-scale range is 200mV to 900mV. |
| 11 | VOUT | input | Output voltage sense and low-noise control input; decouple with a minimum 1µF capacitor, and it must be connected to PVOUT in the application. |
| 12 | PVOUT | power_out | Power output for the buck-boost converter; connect a minimum 68µF low ESR capacitor to PGND as close to the device as possible, and connect it to VOUT in the application. |
| 13 | SW2 | output | Buck-boost converter switch pin; connect the inductor between SW1 and SW2. |
| 14 | PGND | power_in | Power ground connection that must make full connection to the PCB ground plane to meet the specified thermal requirements, and it must be connected to GND in the application. |
| 15 | PGND | power_in | Power ground connection that must make full connection to the PCB ground plane to meet the specified thermal requirements, and it must be connected to GND in the application. |
| 16 | SW1 | output | Buck-boost converter switch pin; connect the inductor between SW1 and SW2. |
| 17 | PGND | power_in | Exposed thermal pad that is the power ground connection and must be soldered to the PCB ground plane to meet the specified thermal performance. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Operating Voltage | | 1.8 | | 5.5 | V | EN/UVLO > 1.24V | 3 |
| VOUT Operating Voltage | | 1.8 | | 5.5 | V | Adjustable Version with External Divider | 3 |
| Feedback Voltage | | 0.98 | 1 | 1.02 | V | | 3 |
| Sleep Quiescent Current, VIN | | | 15 | 25 | µA | SYNC/MODE = 0V, VOUT in Regulation, Non-Switching | 3 |
| Sleep Quiescent Current, VOUT | | | 1 | 2 | µA | SYNC/MODE = 0V | 3 |
| Shutdown Current, VIN | | | 0.5 | 2 | µA | EN/UVLO = 0V, SS = 0V (Note 7) | 3 |
| Current in UVLO, VIN | | | 8 | 25 | µA | EN/UVLO = 1.05V | 3 |
| EN/UVLO Pin Rising Threshold | | 1.16 | 1.2 | 1.24 | V | | 3 |
| EN/UVLO Pin Falling Threshold | | 1.06 | 1.1 | 1.14 | V | | 3 |
| EN/UVLO Pin Input Leakage Current | | | 1 | 50 | nA | EN/UVLO = 5V | 3 |
| EN/UVLO Pin Shutdown Threshold | | 0.2 | 0.75 | 1.05 | V | EN/UVLO Pin Voltage | 3 |
| Average Inductor Current Limit | | 5.5 | 6.5 | 8.7 | A | | 3 |
| Peak Inductor Current Limit | | 8 | 9.5 | 11 | A | | 3 |
| IZERO Current | | -0.25 | 0 | 0.25 | A | SYNC/MODE = 0V | 3 |
| Reverse Inductor Current Limit | | -1.5 | -1.2 | -0.9 | A | SYNC/MODE = 3.6V | 3 |
| Lowside MOSFETs Leakage Currents | | | 0.05 | 2 | µA | VSW = 5.5V, EN/UVLO = 0 | 3 |
| Highside MOSFETs Leakage Current | | | 0.1 | 10 | µA | VIN = VOUT = 5.5V, VSW1 = VSW2 = 0V, EN/UVLO = 0 | 3 |
| Switching Frequency | | 1.8 | 2.2 | 2.6 | MHz | RT to VIN or RT = 49.9kΩ | 3 |
| Switching Frequency Range | | 0.4 | | 4 | MHz | RT Programmable | 3 |
| Max Boost Duty Cycle (SW2 Low) | | 83 | 88 | 93 | % | RT = VIN, FB or VOUT 5% Below Regulation Value | 3 |
| SYNC/MODE Applied Clock Frequency | | 0.5 | | 4 | MHz | RT Chosen to Program a 25% Lower Frequency | 3 |
| SYNC/MODE Input High Logic Level | | 1.5 | | | V | | 3 |
| SYNC/MODE Input Low Logic Level | | | | 0.5 | V | | 3 |
| SYNC/MODE Input Leakage Current | | | 1 | 50 | nA | SYNC/MODE = 5V | 3 |
| Feedback Pin Input Current | | | 0 | 50 | nA | FB = 1V | 3 |
| VC Source/Sink Current | | -12 | | 12 | µA | FB = 0.9V Source, FB = 1.1V Sink | 3 |
| PWM Mode No-Load Current, VIN | | | 20 | | mA | | 3 |
| Lowside (B & C) MOSFET RDS(ON) | | | 18 | | mΩ | VIN = 3.6V, VOUT = 3.0V | 3 |
| Highside (A & D) MOSFET RDS(ON) | | | 25 | | mΩ | VIN = VOUT = 3.6V | 3 |
| Min Duty Cycle (SW1 High) | | | 0 | | % | RT = VIN, FB or VOUT 5% Above Regulation Value | 3 |
| SYNC/MODE High or Low Pulse Width | | | 75 | | ns | | 3 |
| Soft-Start Period (CSS Charge Time to 0.8V) | | | 2.2 | | ms | SS = VIN or CSS = 2.7nF | 3 |
| External SS Regulation Voltage | | | 1 | | V | Capacitor to GND Sets SS Time | 3 |
| Error Amplifier Transconductance | | | 110 | | µS | VC Current = ±4µA | 3 |
| Supply Voltages (PVIN, VIN, PVOUT, VOUT) | | -0.3 | | 6 | V | | 2 |
| SW1, SW2 Voltage DC | | -0.3 | | 6 | V | DC | 2 |
| SW1, SW2 Voltage Pulsed | | -1 | | 7 | V | PULSED (< 100ns) | 2 |
| All Other Pins Voltage | | -0.3 | | 6 | V | | 2 |
| Operating Junction Temperature Range (LT3154E/LT3154I) | | -40 | | 125 | °C | | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 2 |
| Thermal Resistance Junction-to-Ambient (demoboard) | θJA | | 22 | | °C/W | DEMOBOARD | 2 |
| Thermal Resistance Junction-to-Case | θJC | | 9 | | °C/W | | 2 |
| Thermal Resistance Junction-to-Ambient (JEDEC) | θJA | | 42 | | °C/W | JEDEC (Note 5) | 2 |
## CAD (KiCad official)
- Symbol: `LT3154AV#PBF`
- Footprint: `Package_DFN_QFN:LQFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `lt3154av-pbf-etched.step` / `lt3154av-pbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lt3154av-pbf.step` / `lt3154av-pbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907260908482560) (32 pp, sha256 `297cf4adc4d1d32a`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lt3154av-pbf-datasheet.pdf)