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LT3094EDD#PBF
Public Made by Adomby adom
Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WDFN-12-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LT3094EDD#PBF
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WDFN-12-EP(3x3)
LT3094EDD#PBF from Analog Devices, in a WDFN-12-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input pin that supplies power to the regulator; a bypass capacitor is required at IN and a minimum 10µF IN capacitor is needed for stability. |
| 2 | IN | power_in | Input pin that supplies power to the regulator; a bypass capacitor is required at IN and a minimum 10µF IN capacitor is needed for stability. |
| 3 | EN/UV | bidirectional | Enable/UVLO pin that shuts the part down when pulled low, can be switched with positive or negative voltages (turn-on at about 1.26V above or below ground), and must not be left floating (tie to IN if unused). |
| 4 | PG | output | Open-collector power good flag that pulls low when PGFB is between 0V and -300mV, may be left floating if unused, and remains valid in shutdown. |
| 5 | PGFB | input | Power good feedback pin that sets the programmable power good threshold via an external divider and activates fast start-up; tie to IN if power good and fast start-up are not used. |
| 6 | ILIM | input | Current limit programming pin where a resistor to GND sets the limit with a nominal scale factor of 3.75A·kΩ, Kelvin connected to GND for best accuracy; tie to GND if unused and do not float. |
| 7 | VIOC | output | Voltage for Input-to-Output Control pin, the output of a unity-gain amplifier that sinks at least 100µA to control an upstream regulator; float if unused. |
| 8 | SET | input | Inverting input of the error amplifier and regulation setpoint that sinks a precision 100µA through RSET, with output voltage VSET = ISET · RSET over a range of 0V to -19.5V; Kelvin connect its ground side to the load. |
| 9 | GND | power_in | Ground pin for the regulator. |
| 10 | OUTS | input | Output sense pin, the noninverting input of the error amplifier that should be Kelvin connected to the output capacitor and load; must not be driven more than 0.3V below IN. |
| 11 | OUT | power_out | Output pin that supplies power to the load and requires a minimum 10µF output capacitor with ESR below 30mΩ and ESL below 1.5nH; must not be driven more than 0.3V below IN. |
| 12 | OUT | power_out | Output pin that supplies power to the load and requires a minimum 10µF output capacitor with ESR below 30mΩ and ESL below 1.5nH; must not be driven more than 0.3V below IN. |
| 13 | IN | power_in | Exposed pad, internally connected to IN, which must be soldered to the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | WDFN-12-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 13 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | -20 | -2.3 | V | ILOAD = 500mA | 4 | ||
| Minimum IN Pin Voltage (Note 8) | -2.3 | -1.8 | V | ILOAD = 500mA, VIN UVLO Rising | 4 | ||
| SET Pin Current | ISET | 99 | 100 | 101 | µA | VIN = -2.3V, ILOAD = 1mA, VOUT = -1.5V | 4 |
| SET Pin Current | ISET | 98 | 100 | 102 | µA | -20V < VIN < -2.3V, -19.5V < VOUT <0V, 1mA < ILOAD <500mA (Note 7) | 4 |
| Output Offset Voltage VOS (VOUT, VSET) (Note 9) | VOS | -1 | 1 | mV | VIN = -2.3V, ILOAD = 1mA, VOUT = -1.5V | 4 | |
| Output Offset Voltage VOS (VOUT, VSET) (Note 9) | VOS | -2 | 2 | mV | -20V < VIN < -2.3V, -19.5V < VOUT <0V, 1mA < ILOAD <500mA (Note 7) | 4 | |
| Line Regulation: ∆ISET | ∆ISET | -5 | 0.5 | 5 | nA/V | VIN = -2.3V to -20V, ILOAD = 1mA, VOUT = -1.5V | 4 |
| Line Regulation: ∆VOS | ∆VOS | -6 | 0.1 | 6 | µV/V | VIN = -2.3V to -20V, ILOAD = 1mA, VOUT = -1.5V (Note 9) | 4 |
| Load Regulation: ∆VOS | ∆VOS | 0.03 | 0.5 | mV | ILOAD = 1mA to 500mA, VIN = -2.3V, VOUT = -1.5V (Note 9) | 4 | |
| Change in ISET with VSET | ISET | 100 | 850 | nA | VSET = -1.5V to -19.5V, VIN = -20V, ILOAD = 1mA | 4 | |
| Change in VOS with VSET | VOS | 0.02 | 0.5 | mV | VSET = -1.5V to -19.5V, VIN = -20V, ILOAD = 1mA (Note 9) | 4 | |
| Change in ISET with VSET | ISET | 150 | 500 | nA | VSET = 0V to -1.5V, VIN = -20V, ILOAD = 1mA | 4 | |
| Change in VOS with VSET | VOS | 0.15 | 2 | mV | VSET = 0V to -1.5V, VIN = -20V, ILOAD = 1mA (Note 9) | 4 | |
| Dropout Voltage (Note 10) | 185 | 225 | 275 | mV | ILOAD = 1mA, 50mA | 4 | |
| Dropout Voltage (Note 10) | 185 | 230 | 280 | mV | ILOAD = 100mA | 4 | |
| Dropout Voltage (Note 10) | 235 | 310 | 410 | mV | ILOAD = 500mA | 4 | |
| GND Pin Current (Note 11) | 2.4 | 4 | mA | VIN = VOUT(NOMINAL), ILOAD = 1mA | 4 | ||
| GND Pin Current (Note 11) | 3.1 | 5.5 | mA | VIN = VOUT(NOMINAL), ILOAD = 50mA | 4 | ||
| GND Pin Current (Note 11) | 3.8 | 6.5 | mA | VIN = VOUT(NOMINAL), ILOAD = 100mA | 4 | ||
| GND Pin Current (Note 11) | 12 | 23 | mA | VIN = VOUT(NOMINAL), ILOAD = 500mA | 4 | ||
| Positive EN/UV Trip Point Rising (Turn-On) | 1.2 | 1.26 | 1.35 | V | VIN = -2.3V | 5 | |
| Negative EN/UV Trip Point Rising (Turn-On) | -1.33 | -1.26 | -1.2 | V | VIN = -2.3V | 5 | |
| Quiescent Current in Shutdown (VEN/UV = 0V) | 3 | 8 | µA | VIN = -6V, VPG = Open | 5 | ||
| Internal Current Limit (Note 14) | 550 | 750 | mA | VIN = -2.3V, VOUT = 0V | 5 | ||
| Internal Current Limit (Note 14) | 40 | 425 | mA | VIN = -12V, VOUT = 0V | 5 | ||
| Internal Current Limit (Note 14) | 85 | 160 | mA | VIN = -20V, VOUT = 0V | 5 | ||
| Programmable Current Limit | 450 | 500 | 560 | mA | VIN = -2.3V, VOUT = 0V, RILIM = 7.5kΩ | 5 | |
| Programmable Current Limit | 90 | 105 | 120 | mA | VIN = -2.3V, VOUT = 0V, RILIM = 37.5kΩ | 5 | |
| PGFB Trip Point Rising | 288 | 300 | 312 | mV | 5 | ||
| PGFB Pin Current | 30 | 100 | nA | VIN = -2.3V, VPGFB = -300mV | 5 | ||
| PG Output Low Voltage | 17 | 50 | mV | IPG = 100µA | 5 | ||
| PG Leakage Current | 1 | µA | VPG = 20V | 5 | |||
| VIOC Maximum Output Voltage Swing | -1.35 | -1.2 | V | VIN, VOUT = -2V, VOUT ≤ -1.5V | 5 | ||
| VIOC Sink Current | 100 | µA | VIN, VOUT = -2V, VVIOC = -1V | 5 | |||
| Minimum Load Current (Note 16) | 10 | µA | VOUT > -1.5V | 6 | |||
| IN Pin Voltage with Respect to GND | VIN | -22 | 0.3 | V | with respect to GND Pin | 3 | |
| EN/UV Pin Voltage with Respect to IN Pin | VEN/UV | -0.3 | 30 | V | with respect to IN Pin (Note 2) | 3 | |
| EN/UV Pin Voltage with Respect to GND Pin | VEN/UV | -22 | 22 | V | with respect to GND Pin | 3 | |
| PG Pin Voltage with Respect to IN Pin | VPG | -0.3 | 30 | V | with respect to IN Pin (Note 2) | 3 | |
| PG Pin Voltage with Respect to GND Pin | VPG | -0.3 | 22 | V | with respect to GND Pin | 3 | |
| PGFB Pin Voltage with Respect to IN Pin | VPGFB | -0.3 | 30 | V | with respect to IN Pin (Note 2) | 3 | |
| PGFB Pin Voltage with Respect to GND Pin | VPGFB | -22 | 22 | V | with respect to GND Pin | 3 | |
| ILIM Pin Voltage with Respect to IN Pin | VILIM | -0.3 | 22 | V | with respect to IN Pin (Note 2) | 3 | |
| VIOC Pin Voltage with Respect to IN Pin | VVIOC | -0.3 | 22 | V | with respect to IN Pin (Note 2) | 3 | |
| VIOC Pin Voltage with Respect to GND Pin | VVIOC | -2 | 0.3 | V | with respect to GND Pin | 3 | |
| SET Pin Voltage with Respect to IN Pin | VSET | -0.3 | 22 | V | with respect to IN Pin (Note 2) | 3 | |
| SET Pin Voltage with Respect to GND Pin | VSET | -22 | 22 | V | with respect to GND Pin | 3 | |
| SET Pin Current (Note 4) | ISET | -10 | 10 | mA | Note 4 | 3 | |
| OUTS Pin Voltage with Respect to IN Pin | VOUTS | -0.3 | 22 | V | with respect to IN Pin (Note 2) | 3 | |
| OUTS Pin Voltage with Respect to GND Pin | VOUTS | -22 | 22 | V | with respect to GND Pin | 3 | |
| OUTS Pin Current (Note 4) | IOUTS | -10 | 10 | mA | Note 4 | 3 | |
| OUT Pin Voltage with Respect to IN Pin | VOUT | -0.3 | 22 | V | with respect to IN Pin (Note 2) | 3 | |
| OUT Pin Voltage with Respect to GND Pin | VOUT | -22 | 22 | V | with respect to GND Pin | 3 | |
| Operating Junction Temperature Range (E-, I-Grades) | TJ | -40 | 125 | °C | E-, I-Grades | 3 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Thermal Resistance Junction-to-Ambient (DD package, DFN) | θJA | 34 | °C/W | DD package (12-lead 3mm × 3mm DFN), TJMAX = 150°C | 3 | ||
| Thermal Resistance Junction-to-Case (DD package, DFN) | θJC | 5.5 | °C/W | DD package (12-lead 3mm × 3mm DFN), TJMAX = 150°C | 3 | ||
| Minimum Output Capacitor (ceramic) | COUT | 10 | µF | 15 | |||
| Output Capacitor ESR | ESR | 30 | mΩ | Output capacitor (COUT) for stability | 15 | ||
| Output Capacitor ESL | ESL | 1.5 | nH | Output capacitor (COUT) for stability | 15 |
CAD (KiCad official)
- Symbol:
LT3094EDD#PBF - Footprint:
Package_DFN_QFN:WDFN-12-1EP_3x3mm_P0.45mm_EP1.7x2.5mm - 3D model: WDFN-12-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lt3094edd-pbf-etched.step/lt3094edd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3094edd-pbf.step/lt3094edd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (34 pp, sha256
c82438ca3359a588, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).