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README

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LT3090IDD#TRPBF

Analog Devices · Linear Voltage Regulators (LDO) · WDFN-10-EP(3x3)

LT3090IDD#TRPBF from Analog Devices, in a WDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input pin that supplies power to the regulator; all IN pins must be tied together and the LT3090 requires an input bypass capacitor, typically 2.2µF to 4.7µF.
2 IN power_in Input pin that supplies power to the regulator; all IN pins must be tied together and the LT3090 requires an input bypass capacitor, typically 2.2µF to 4.7µF.
3 ILIM input Current limit programming pin where a resistor between ILIM and IN sets the limit with a nominal 10A•kΩ scale factor, and ILIM must not be driven more than 0.3V below IN.
4 IMONP passive Positive current monitor pin that sources 1/2000 of output current through a resistor to GND, and must not be driven more than 0.3V below IN; tie to IN if unused.
5 IMONN passive Negative current monitor pin that sinks 1/1000 of output current through a resistor to GND, must be at least 2V above IN and IMONP when used, and must not be driven more than 0.3V below IN; tie to GND if unused.
6 SHDN input Bidirectional shutdown pin where the output is off within ±0.45V of GND and on beyond ±1.4V, with a maximum pin current of 7µA out (negative logic) or 30µA in (positive logic), and it must not be floated or driven more than 0.3V below IN.
7 SET input Inverting error amplifier input and regulation setpoint that receives a precision 50µA current, where a resistor to GND programs the output voltage and the pin must not be driven more than 0.3V below IN.
8 GND power_in Ground pin that supplies the quiescent current and NPN pass transistor drive current, and must not be driven more than 0.3V below IN.
9 OUT power_out Output pin that supplies power to the load; all OUT pins should be tied together, with a minimum 4.7µF output capacitor of ESR less than 0.5Ω and a minimum 10µA load current for stability.
10 OUT power_out Output pin that supplies power to the load; all OUT pins should be tied together, with a minimum 4.7µF output capacitor of ESR less than 0.5Ω and a minimum 10µA load current for stability.
11 IN power_in Exposed backside pad that is an electrical connection to IN and the device substrate and must be soldered to the PCB for proper electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package WDFN-10-EP(3x3)
Category Power Management ICs
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN pin voltage with respect to GND -40 0.3 V Note 3; printed as '0.3V, -40V', sign of 0.3V not clear in extraction 2
ILIM pin voltage with respect to IN pin -0.3 0.7 V with respect to IN pin (Note 3) 2
IMONP pin voltage with respect to IN pin -0.3 40 V with respect to IN pin (Note 3) 2
IMONP pin voltage with respect to GND pin -40 20 V with respect to GND pin 2
IMONP pin voltage with respect to IMONN pin -40 20 V with respect to IMONN pin 2
IMONN pin voltage with respect to IN pin -0.3 40 V with respect to IN pin (Note 3) 2
IMONN pin voltage with respect to GND pin -40 20 V with respect to GND pin 2
SHDN pin voltage with respect to IN pin -0.3 55 V with respect to IN pin (Note 1, Note 3) 2
SHDN pin voltage with respect to GND pin -40 20 V with respect to GND pin (Note 1) 2
SET pin voltage with respect to IN pin -0.3 36 V with respect to IN pin (Note 3) 2
SET pin voltage with respect to GND pin -36 36 V with respect to GND pin, printed ±36V 2
SET pin current -5 5 mA Note 9, printed ±5mA 2
OUT pin voltage with respect to IN pin -0.3 36 V with respect to IN pin (Note 3) 2
OUT pin voltage with respect to GND pin -36 36 V with respect to GND pin, printed ±36V 2
Operating junction temperature range (E-, I-Grade) TJ -40 125 °C E-, I-Grade (Note 2) 2
Maximum junction temperature TJMAX 150 °C DD package 2
Storage temperature range TSTG -65 150 °C 2
SET pin current (ISET), 25°C row ISET 49.5 50 50.5 µA VIN = -1.9V, ILOAD = 1mA, -36V < VIN < -1.9V, 1mA < ILOAD < 600mA (Note 5) 3
SET pin current (ISET), full operating temperature range ISET 49 50 51 µA VIN = -1.9V, ILOAD = 1mA, -36V < VIN < -1.9V, 1mA < ILOAD < 600mA (Note 5); l = full temperature range 3
Output offset voltage (VOUT, VSET), 25°C row VOS -1 1 mV VIN = -1.9V, ILOAD = 1mA, -36V < VIN < -1.9V, 1mA < ILOAD < 600mA (Note 5) 3
Output offset voltage (VOUT, VSET), full operating temperature range VOS -2 2 mV VIN = -1.9V, ILOAD = 1mA, -36V < VIN < -1.9V, 1mA < ILOAD < 600mA (Note 5); l = full temperature range 3
Load regulation ΔVOS ΔVOS 1.2 2.5 mV ILOAD = 1mA to 600mA, VIN = -1.9V (Note 6); l = full temperature range 3
Output regulation with SET pin voltage change ΔISET/ΔVSET ΔISET/ΔVSET 0.2 1 nA/V VSET = 0V to -32V, VIN = -36V, ILOAD = 1mA; l = full temperature range 3
Output regulation with SET pin voltage change ΔVOS/ΔVSET ΔVOS/ΔVSET 2.5 30 µV/V VSET = 0V to -32V, VIN = -36V, ILOAD = 1mA; l = full temperature range 3
GND pin current at ILOAD = 10µA IGND 1 1.4 mA VIN = VOUT(NOMINAL) (Note 8), ILOAD = 10µA; l = full temperature range 3
GND pin current at ILOAD = 1mA IGND 1.05 1.4 mA VIN = VOUT(NOMINAL) (Note 8), ILOAD = 1mA; l = full temperature range 3
GND pin current at ILOAD = 100mA IGND 2.6 5 mA VIN = VOUT(NOMINAL) (Note 8), ILOAD = 100mA; l = full temperature range 3
GND pin current at ILOAD = 600mA IGND 11.5 22.5 mA VIN = VOUT(NOMINAL) (Note 8), ILOAD = 600mA; l = full temperature range 3
Quiescent current in shutdown 0.1 1 µA VIN = -6V, VSHDN = 0V 3
Quiescent current in shutdown, full operating temperature range 10 µA VIN = -6V, VSHDN = 0V; l = full temperature range 3
SHDN pin current at VSHDN = 0V ISHDN -1 1 µA VSHDN = 0V (Note 10); printed ±1 3
SHDN pin current at VSHDN = 15V ISHDN 21 30 µA VSHDN = 15V (Note 10) 3
SHDN pin current at VSHDN = -15V ISHDN -7 -4.5 µA VSHDN = -15V (Note 10) 3
SHDN pin positive turn-ON threshold 1.14 1.23 1.32 V Positive SHDN rising; l = full temperature range 3
SHDN pin negative turn-ON threshold (in magnitude) -1.36 -1.27 -1.18 V Negative SHDN rising (in magnitude); l = full temperature range 3
Internal current limit at VIN = -1.9V, VOUT = 0V 650 750 850 mA VIN = -1.9V, VOUT = 0V (Note 13); l = full temperature range 3
Internal current limit at VIN = -1.9V, ΔVOUT < 10mV 630 730 830 mA VIN = -1.9V, ΔVOUT < 10mV; l = full temperature range 3
Programming scale factor (programmable current limit) 460 500 540 A•kΩ -36V < VIN < -1.9V, IOUT > 50mA (Note 14); l = full temperature range 3
Max IOUT with RILIM = 100k 85 100 115 mA VIN = -1.9V, RILIM = 100k; l = full temperature range 3
Positive current monitoring (IMONP) scale factor at IOUT = 600mA 280 300 320 mA/A IOUT = 600mA, VIN = -2.5V, VIMONN = 2V, VIMONP = 0V; l = full temperature range 4
IMONP pin current at IOUT = 100mA IMONP 42.5 50 57.5 µA IOUT = 100mA, VIN = -2.5V, VIMONN = 2V, VIMONP = 0V; l = full temperature range 4
Negative current monitoring (IMONN) scale factor at IOUT = 600mA 560 600 640 mA/A IOUT = 600mA, VIN = -2.5V, VIMONN = 0V, VIMONP = -2.5V; l = full temperature range 4
IMONN pin current at IOUT = 100mA IMONN 85 100 115 µA IOUT = 100mA, VIN = -2.5V, VIMONN = 0V, VIMONP = -2.5V; l = full temperature range 4
Minimum required load current 10 µA -36V < VIN < -1.9V (Note 4); l = full temperature range 4
Ripple rejection, 120Hz 70 85 dB VIN, VOUT = -1.5V (Avg), VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 100mA, COUT = 4.7µF, CSET = 0.47µF 3
Thermal resistance junction-to-ambient (DD package) θJA 34 °C/W DD package, printed in Pin Configuration 2
Thermal resistance junction-to-case (DD package) θJC 5.5 °C/W DD package, printed in Pin Configuration 2

CAD (KiCad official)

  • Symbol: LT3090IDD#TRPBF
  • Footprint: Package_DFN_QFN:WDFN-10-1EP_3x3mm_P0.5mm_EP1.8x2.5mm
  • 3D model: WDFN-10-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: lt3090idd-trpbf-etched.step / lt3090idd-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3090idd-trpbf.step / lt3090idd-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 a02e3baeccf7ef6c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF