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LT3071EUFD#PBF

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Analog Devices Linear Voltage Regulators (LDO), QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT3071EUFD#PBF

Analog Devices · Linear Voltage Regulators (LDO) · QFN-28-EP(4x5)

LT3071EUFD#PBF from Analog Devices, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIOC output Output of the tracking function that drives the buck regulator to hold the LT3071 input at VOUT + 300mV, to maximize efficiency and minimize power dissipation.
2 PWRGD output Open-drain NMOS power-good output that pulls low on VOUT below 90% of nominal on rising edge, VOUT below 85% for more than 25µs, junction above about 145°C, VBIAS below UVLO, or OUT-to-IN reverse current.
3 REF/BYP output Output of the bandgap reference with approximately 19kΩ impedance that must not be externally loaded; a 10nF bypass to GND decreases output noise and provides reference soft-start.
4 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
5 IN power_in Input supply to the high current pass transistor; all IN pins must be tied together and bypassed with at least 47µF.
6 IN power_in Input supply to the high current pass transistor; all IN pins must be tied together and bypassed with at least 47µF.
7 IN power_in Input supply to the high current pass transistor; all IN pins must be tied together and bypassed with at least 47µF.
8 IN power_in Input supply to the high current pass transistor; all IN pins must be tied together and bypassed with at least 47µF.
9 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
10 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
11 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
12 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
13 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
14 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
15 OUT power_out Regulated output supplying the load; all OUT pins must be tied together and a minimum 15µF ceramic output capacitance is required for stability.
16 OUT power_out Regulated output supplying the load; all OUT pins must be tied together and a minimum 15µF ceramic output capacitance is required for stability.
17 OUT power_out Regulated output supplying the load; all OUT pins must be tied together and a minimum 15µF ceramic output capacitance is required for stability.
18 OUT power_out Regulated output supplying the load; all OUT pins must be tied together and a minimum 15µF ceramic output capacitance is required for stability.
19 SENSE input Kelvin sense input to the inverting input of the error amplifier, with input current from 50µA typical at VOUT = 0.8V to 300µA typical at VOUT = 1.8V.
20 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
21 IMON output Output current monitor sourcing a current typically equal to IOUT/2500 (400µA per amp of output current); if unused, tie to VBIAS.
22 MARGA input Analog margining input that adjusts VOUT over ±10%: GND gives −10%, 1.2V gives +10%; float it or terminate with 1nF to GND if unused.
23 VO0 input Three-state output voltage select pin that combines with VO1 and VO2 to select VOUT from 0.8V to 1.8V in 50mV steps; logic low threshold is below 250mV.
24 VO1 input Three-state output voltage select pin that combines with VO0 and VO2 to select VOUT from 0.8V to 1.8V in 50mV steps; VOUT is limited to 1.8V maximum by internal override when VO2 is high.
25 VO2 input Three-state output voltage select pin that combines with VO0 and VO1 to select VOUT from 0.8V to 1.8V in 50mV steps; logic high threshold is above VBIAS − 250mV.
26 GND power_in Ground pin that must be tied to exposed pad Pin 29 and the other GND pins for proper electrical and thermal performance.
27 BIAS power_in Bias supply for internal control circuitry and pass transistor drive, requiring 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V) with at least 2.2µF bypass.
28 EN input Enable input that turns the output device on or off; pulling low places the LT3071 in a low power nap mode, and it must connect to BIAS if unused.
29 GND power_in Exposed pad ground that must be soldered to the PCB ground and tied to all GND pins of the package for electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package QFN-28-EP(4x5)
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN, OUT Pin Voltage -0.3 3.3 V 2
BIAS Pin Voltage -0.3 4 V 2
VO2, VO1, VO0 Inputs -0.3 4 V 2
MARGA Input -0.3 4 V 2
EN Input -0.3 4 V 2
SENSE Input -0.3 4 V 2
VIOC, PWRGD, IMON Outputs -0.3 4 V 2
REF/BYP Output -0.3 4 V 2
Operating Junction Temperature LT3071E TJ -40 125 °C LT3071E/LT3071I 2
Storage Temperature Range TSTG -65 150 °C 2
IN Pin Voltage Range VIN 0.95 3 V VIN ≥ VOUT + 150mV, IOUT = 5A 2
BIAS Pin Voltage Range VBIAS 2.2 3.6 V Note 3 2
Thermal Resistance Junction-to-Ambient θJA 30 35 °C/W QFN package, copper area dependent 2
Regulated Output Voltage VOUT 0.792 0.8 0.808 V VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V 2
Regulated Output Voltage VOUT 0.891 0.9 0.909 V VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V 2
Regulated Output Voltage VOUT 0.99 1 1.01 V VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V 2
Regulated Output Voltage VOUT 1.188 1.2 1.212 V VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V 2
Regulated Output Voltage VOUT 1.782 1.8 1.818 V VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V 2
Regulated Output Voltage Margining 9.5 10 10.5 % MARGA = 1.2V 3
Regulated Output Voltage Margining -10.5 -10 -9.5 % MARGA = 0V 3
Line Regulation to VIN 1 mV VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA 3
Line Regulation to VBIAS 2 mV VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA 3
Line Regulation to VBIAS 1 mV VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA 3
Load Regulation -1.5 -3 -5.5 mV ∆IOUT = 10mA to 5A, VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V 3
Load Regulation -2 -4 -7.5 mV ∆IOUT = 10mA to 5A, VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V 3
Load Regulation -2.5 -5 -9 mV ∆IOUT = 10mA to 5A, VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V 3
Load Regulation -3 -7 -13 mV ∆IOUT = 10mA to 5A, VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V 3
Dropout Voltage 20 35 mV VIN = VOUT(NOMINAL), IOUT = 1A, VOUT = 1V 3
Dropout Voltage 50 65 85 mV VIN = VOUT(NOMINAL), IOUT = 2.5A, VOUT = 1V 3
Dropout Voltage 85 120 150 mV VIN = VOUT(NOMINAL), IOUT = 5A, VOUT = 1V 3
SENSE Pin Current 35 50 65 µA VIN = 1.1V, VSENSE = 0.8V, VBIAS = 2.5V 3
SENSE Pin Current 200 300 400 µA VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V 3
Ground Pin Current 0.65 0.9 1.1 mA VIN = 1.3V, VOUT = 1V, IOUT = 10mA 3
Ground Pin Current 1.35 1.8 2.3 mA VIN = 1.3V, VOUT = 1V, IOUT = 5A 3
BIAS Pin Current in Nap Mode 120 300 420 µA EN = Low 3
BIAS Pin Current 0.75 1.08 1.5 mA VIN = 1.3V, VOUT = 1V, IOUT = 10mA 3
BIAS Pin Current 1.25 1.8 2.4 mA VIN = 1.3V, VOUT = 1V, IOUT = 100mA 3
BIAS Pin Current 2 3 4 mA VIN = 1.3V, VOUT = 1V, IOUT = 500mA 3
BIAS Pin Current 2.6 3.8 5 mA VIN = 1.3V, VOUT = 1V, IOUT = 1A 3
BIAS Pin Current 3.5 5.2 7 mA VIN = 1.3V, VOUT = 1V, IOUT = 2.5A 3
BIAS Pin Current 4.5 6.9 10 mA VIN = 1.3V, VOUT = 1V, IOUT = 5A 3
Current Limit 5.1 6.4 7.7 A VIN, VOUT < 0.3V, VBIAS = 3.3V 3
Current Limit 3.2 4.5 5.8 A VIN, VOUT = 1.0V, VBIAS = 3.3V 3
Current Limit 1.2 2.5 4.3 A VIN, VOUT = 1.7V, VBIAS = 3.3V 3
IMON Full-Scale Output Current IMON 1.6 2 2.4 mA IOUT = 5A, VIN, VOUT = 0.3V, VOUT = 0.8V, 1.8V 3
IMON/IOUT Scale IMON/IOUT 340 400 460 µA/A 1A ≤ IOUT ≤ 5A, VIN, VOUT = 0.3V, VOUT = 0.8V, 1.8V 3
Reverse Output Current 300 450 µA VIN = 0V, VOUT = 1.8V 3
PWRGD VOUT Threshold, Rising 87 90 93 % Percentage of VOUT(NOMINAL), VOUT Rising 3
PWRGD VOUT Threshold, Falling 82 85 88 % Percentage of VOUT(NOMINAL), VOUT Falling 3
PWRGD VOL 50 150 mV IPWRGD = 200µA (Fault Condition) 3
VBIAS Undervoltage Lockout Rising 1.1 1.55 2.1 V VBIAS Rising 3
VBIAS Undervoltage Lockout Falling 0.9 1.4 1.7 V VBIAS Falling 3
VIN-VOUT Servo Voltage by VIOC 250 300 350 mV 3
VIOC Output Current, Sourcing 160 235 310 µA VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin 3
VIOC Output Current, Sinking 170 255 340 µA VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin 3
VIL Input Threshold (Logic-0 State) VIL 0.25 V VO2, VO1, VO0, Input Falling 3
Input Current High 25 40 µA VIH = VBIAS = 2.5V, Current Flows Into Pin, VO2, VO1, VO0 4
Input Current Low 25 40 µA VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin, VO2, VO1, VO0 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts COPPER Table 3, UFD Plastic Package, 28-Lead QFN COPPER AREA 22

CAD (KiCad official)

  • Symbol: LT3071EUFD#PBF
  • Footprint: Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: lt3071eufd-pbf-etched.step / lt3071eufd-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3071eufd-pbf.step / lt3071eufd-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 ba06f950eb009d95, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF