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LT3070EUFD#PBF

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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LT3070EUFD#PBF

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-28-EP(4x5)

LT3070EUFD#PBF from Analog Devices, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIOC output Output of the tracking function that drives an external buck regulator to hold the LT3070 input at VOUT + 300mV.
2 PWRGD output Open-drain NMOS power-good output that pulls low if VOUT is below 90% of nominal on its rising edge or below 85% for more than 25µs, junction temperature typically exceeds 145°C, VBIAS is below its UVLO threshold, or the OUT-to-IN reverse-current detector activates.
3 REF/BYP output Bandgap reference output with approximately 19kΩ impedance that must not be externally loaded and may be bypassed to GND with a 10nF capacitor.
4 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
5 IN power_in Input supply to the high-current pass transistor; tie all IN pins together and bypass with at least 47µF, with the IN pin voltage range given as 0.95V to 3.0V.
6 IN power_in Input supply to the high-current pass transistor; tie all IN pins together and bypass with at least 47µF, with the IN pin voltage range given as 0.95V to 3.0V.
7 IN power_in Input supply to the high-current pass transistor; tie all IN pins together and bypass with at least 47µF, with the IN pin voltage range given as 0.95V to 3.0V.
8 IN power_in Input supply to the high-current pass transistor; tie all IN pins together and bypass with at least 47µF, with the IN pin voltage range given as 0.95V to 3.0V.
9 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
10 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
11 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
12 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
13 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
14 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
15 OUT power_out Regulated output that supplies the load; tie all OUT pins together and provide at least 15µF of low-ESR ceramic output capacitance for stability.
16 OUT power_out Regulated output that supplies the load; tie all OUT pins together and provide at least 15µF of low-ESR ceramic output capacitance for stability.
17 OUT power_out Regulated output that supplies the load; tie all OUT pins together and provide at least 15µF of low-ESR ceramic output capacitance for stability.
18 OUT power_out Regulated output that supplies the load; tie all OUT pins together and provide at least 15µF of low-ESR ceramic output capacitance for stability.
19 SENSE input Kelvin sense input to the inverting error amplifier, best connected at the load, with input current typically 50µA at VOUT = 0.8V rising to 300µA at VOUT = 1.8V.
20 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
21 MARGSEL input Three-state margining enable and polarity input: below 250mV enables negative margining, above VBIAS - 250mV enables positive margining, and the Hi-Z window disables margining.
22 MARGTOL input Three-state margining tolerance input selecting ±1% when low (below 250mV), ±5% when high (above VBIAS - 250mV), and ±3% in the Hi-Z window.
23 VO0 input Three-state output voltage select input that combines with VO1 and VO2 to set VOUT from 0.8V to 1.8V in 50mV steps; logic low is below 250mV and logic high is above VBIAS - 250mV.
24 VO1 input Three-state output voltage select input that combines with VO0 and VO2 to set VOUT from 0.8V to 1.8V in 50mV steps; it is overridden internally when VO2 is high so VOUT is limited to 1.8V.
25 VO2 input Three-state output voltage select input that combines with VO0 and VO1 to set VOUT from 0.8V to 1.8V in 50mV steps; when high, it limits VOUT to 1.8V maximum by overriding VO1.
26 GND power_in Ground pin that must be tied to the exposed pad (pin 29) and the other GND pins for electrical and thermal performance.
27 BIAS power_in Bias supply for control circuitry and the pass transistor driver, which must satisfy 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V) and requires at least a 2.2µF bypass capacitor.
28 EN input Enable input that turns the output device on or off, with a maximum rising threshold of 0.56 % of VBIAS, a minimum falling threshold of 0.36 % of VBIAS, and a pull-up resistor that must be less than 35k; connect to BIAS if unused.
29 GND power_in Exposed pad, electrically connected to GND, which must be soldered to the PCB ground and tied to all GND pins for thermal and electrical performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package QFN-28-EP(4x5)
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN Pin Voltage Range 0.95 3 V VIN ≥ VOUT + 150mV, IOUT= 5A 3
BIAS Pin Voltage Range 2.2 3.6 V Note 3 3
Regulated Output Voltage VOUT 0.792 0.8 0.808 V VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V 3
Regulated Output Voltage VOUT 0.891 0.9 0.909 V VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V 3
Regulated Output Voltage VOUT 0.99 1 1.01 V VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V 3
Regulated Output Voltage VOUT 1.089 1.1 1.111 V VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.35V ≤ VIN ≤ 1.55V 3
Regulated Output Voltage VOUT 1.188 1.2 1.212 V VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V 3
Regulated Output Voltage VOUT 1.485 1.5 1.515 V VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.75V ≤ VIN ≤ 1.95V, VBIAS = 3.3V 3
Regulated Output Voltage VOUT 1.782 1.8 1.818 V VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V 3
Regulated Output Voltage Margining 0.8 1 1.2 % MARGTOL = 0V, MARGSEL = VBIAS 3
Regulated Output Voltage Margining -1.2 -1 -0.8 % MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA 3
Regulated Output Voltage Margining 2.7 3 3.3 % MARGTOL = FLOAT, MARGSEL = VBIAS 3
Regulated Output Voltage Margining -3.3 -3 -2.7 % MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA 3
Regulated Output Voltage Margining 4.6 5 5.4 % MARGTOL = VBIAS, MARGSEL = VBIAS 3
Regulated Output Voltage Margining -5.4 -5 -4.6 % MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA 3
Line Regulation to VIN 1 mV VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA 3
Line Regulation to VBIAS 2 mV VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA 3
Line Regulation to VBIAS 1 mV VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA 3
Load Regulation -1.5 -3 -5.5 mV ∆IOUT = 10mA to 5A, VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V 3
Load Regulation -2 -4 -7.5 mV ∆IOUT = 10mA to 5A, VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V 3
Load Regulation -2.5 -5 -9 mV ∆IOUT = 10mA to 5A, VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V 3
Load Regulation -3 -7 -13 mV ∆IOUT = 10mA to 5A, VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V 3
Dropout Voltage 20 35 mV VIN = VOUT(NOMINAL) (Note 6), IOUT = 1A, VOUT = 1V 3
Dropout Voltage 50 65 85 mV VIN = VOUT(NOMINAL) (Note 6), IOUT = 2.5A, VOUT = 1V 3
Dropout Voltage 85 120 150 mV VIN = VOUT(NOMINAL) (Note 6), IOUT = 5A, VOUT = 1V 3
SENSE Pin Current 35 50 65 µA VIN = 1.1V, VSENSE = 0.8V 3
SENSE Pin Current 200 300 400 µA VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V 3
Ground Pin Current 0.65 1.1 1.8 mA VIN = 1.3V, VOUT = 1V, IOUT = 10mA 4
Ground Pin Current 0.9 1.35 2.3 mA VIN = 1.3V, VOUT = 1V, IOUT = 5A 4
BIAS Pin Current in Nap Mode 120 200 320 µA EN = Low 4
BIAS Pin Current 0.75 1.08 1.5 mA VIN = 1.3V, VOUT = 1V, IOUT = 10mA 4
BIAS Pin Current 1.25 1.8 2.4 mA VIN = 1.3V, VOUT = 1V, IOUT = 100mA 4
BIAS Pin Current 2 3 4 mA VIN = 1.3V, VOUT = 1V, IOUT = 500mA 4
BIAS Pin Current 2.6 3.8 5 mA VIN = 1.3V, VOUT = 1V, IOUT = 1A 4
BIAS Pin Current 3.5 5.2 7 mA VIN = 1.3V, VOUT = 1V, IOUT = 2.5A 4
BIAS Pin Current 4.5 6.9 10 mA VIN = 1.3V, VOUT = 1V, IOUT = 5A 4
Current Limit 5.1 6.4 7.7 A VIN, VOUT < 0.3V, VBIAS = 3.3V 4
Current Limit 3.2 4.5 5.8 A VIN, VOUT = 1.0V, VBIAS = 3.3V 4
Current Limit 1.2 2.5 4.3 A VIN, VOUT = 1.7V, VBIAS = 3.3V 4
Reverse Output Current 300 450 µA VIN = 0V, VOUT = 1.8V (Note 8) 4
PWRGD VOUT Threshold (rising) 87 90 93 % Percentage of VOUT(NOMINAL), VOUT Rising 4
PWRGD VOUT Threshold (falling) 82 85 88 % Percentage of VOUT(NOMINAL), VOUT Falling 4
PWRGD VOL 50 150 mV IPWRGD = 200µA (Fault Condition) 4
VBIAS Undervoltage Lockout (rising) 1.1 1.55 2.1 V VBIAS Rising 4
VBIAS Undervoltage Lockout (falling) 0.9 1.4 1.7 V VBIAS Falling 4
VIN-VOUT Servo Voltage by VIOC 250 300 350 mV 4
VIOC Output Current 160 235 310 µA VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin 4
VIOC Output Current 170 255 340 µA VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin 4
VIL Input Threshold (Logic-0 State) VIL 0.25 V Input Falling; VO2, VO1, VO0, MARGSEL, MARGTOL 4
Input Current High 25 40 µA VIH = VBIAS = 2.5V, Current Flows Into Pin; VO2, VO1, VO0, MARGSEL, MARGTOL 4
Input Current Low 25 40 µA VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin; VO2, VO1, VO0, MARGSEL, MARGTOL 4
EN Pin Logic High Current 2.5 4 6.5 µA VEN = VBIAS = 2.5V 4
EN Pin Logic Low Current 0.1 µA VEN = 0V 5
IN, OUT pins voltage (absolute maximum) -0.3 3.3 V 2
BIAS, VO2, VO1, VO0, MARGSEL, MARGTOL, EN, SENSE, VIOC, PWRGD, REF/BYP pins voltage (absolute maximum) -0.3 4 V 2
Operating Junction Temperature (LT3070E) TJ -40 125 °C LT3070E/LT3070I (Note 2) 2
Storage Temperature Range -65 150 °C 2
Thermal Resistance, Junction-to-Ambient (UFD 28-lead QFN) θJA 30 35 °C/W TJMAX = 125°C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts COPPER Table 3, UFD Plastic Package, 28-Lead QFN COPPER AREA 23

CAD (KiCad official)

  • Symbol: LT3070EUFD#PBF
  • Footprint: Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: lt3070eufd-pbf-etched.step / lt3070eufd-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3070eufd-pbf.step / lt3070eufd-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 59f97ca88b397a7c, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF