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LT3045IDD#PBF
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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Datasheet
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README
markdownLT3045IDD#PBF
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10-EP(3x3)
LT3045IDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin that powers the regulator, requires a bypass capacitor (4.7µF minimum input capacitor stated) and withstands reverse voltages relative to GND, OUTS and OUT. |
| 2 | IN | power_in | Second input supply pin, tied to the same input net as pin 1, with the same bypass and reverse-voltage requirements as IN. |
| 3 | EN/UV | input | Enable and undervoltage-lockout pin where pulling low forces shutdown (<1µA quiescent), the regulator turns on at 1.24V rising with 130mV hysteresis, and the pin must not be left floating. |
| 4 | PG | output | Open-collector power-good flag that pulls low when PGFB is below 300mV and must not be driven more than 0.3V below GND; float the pin if power good is unused. |
| 5 | ILIM | passive | Current-limit programming pin where a resistor to GND sets the limit with a 150mA•kΩ scale factor, it doubles as a 0V to 300mV current monitor, and it should be tied to GND if unused. |
| 6 | PGFB | input | Power-good feedback input where PG releases high when PGFB rises above 300mV (7mV falling hysteresis), and it should be tied to IN if power good and fast start-up are not used. |
| 7 | SET | passive | Error amplifier inverting input and output set-point pin that sources a 100µA current through the external resistor to GND, giving VOUT = ISET·RSET over a 0V to 15V output range. |
| 8 | GND | power_in | Ground connection for the regulator that must be tied directly to the exposed backside pad. |
| 9 | OUTS | input | Output sense pin that is the non-inverting error amplifier input and should be Kelvin-connected directly to the output capacitor and load, with a substrate diode to GND that must not be driven more than 0.3V below GND. |
| 10 | OUT | power_out | Regulator output that supplies the load and requires a minimum 10µF output capacitor with ESR below 20mΩ and ESL below 2nH for stability. |
| 11 | GND | power_in | Exposed backside pad that is the electrical GND connection and must be soldered to the PCB ground and tied directly to the GND pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2 | 20 | V | 3 | ||
| Output Voltage Range | VOUT | 0 | 15 | V | VIN > VOUT | 3 | |
| Minimum IN Pin Voltage | VIN | 1.78 | 2 | V | ILOAD = 500mA, VIN UVLO Rising | 3 | |
| SET Pin Current | ISET | 99 | 100 | 101 | µA | VIN = 2V, ILOAD = 1mA, VOUT = 1.3V | 3 |
| SET Pin Current | ISET | 98 | 100 | 102 | µA | 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) | 3 |
| Output Offset Voltage VOS (VOUT, VSET) | VOS | -1 | 1 | mV | VIN = 2V, ILOAD = 1mA, VOUT = 1.3V | 3 | |
| Output Offset Voltage VOS (VOUT, VSET) | VOS | -2 | 2 | mV | 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) | 3 | |
| Line Regulation ΔISET | ΔISET | -2 | 0.5 | 2 | nA/V | VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V | 3 |
| Line Regulation ΔVOS | ΔVOS | -3 | 0.5 | 3 | µV/V | VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) | 3 |
| Load Regulation ΔVOS | ΔVOS | 0.1 | 0.5 | mV | ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V (Note 4) | 3 | |
| Change in ISET with VSET | ΔISET | 30 | 400 | nA | VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA | 3 | |
| Change in VOS with VSET | ΔVOS | 0.03 | 0.6 | mV | VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) | 3 | |
| Change in ISET with VSET | ΔISET | 150 | 600 | nA | VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA | 3 | |
| Change in VOS with VSET | ΔVOS | 0.3 | 2 | mV | VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) | 3 | |
| Dropout Voltage | VDO | 220 | 330 | mV | ILOAD = 1mA, 50mA | 3 | |
| Dropout Voltage | VDO | 220 | 350 | mV | ILOAD = 300mA (Note 5) | 3 | |
| Dropout Voltage | VDO | 260 | 450 | mV | ILOAD = 500mA (Note 5) | 3 | |
| GND Pin Current | IGND | 2.2 | 4 | mA | VIN = VOUT(NOMINAL), ILOAD = 10µA (Note 6) | 3 | |
| GND Pin Current | IGND | 2.4 | 5.5 | mA | VIN = VOUT(NOMINAL), ILOAD = 1mA (Note 6) | 3 | |
| GND Pin Current | IGND | 3.5 | 7 | mA | VIN = VOUT(NOMINAL), ILOAD = 50mA (Note 6) | 3 | |
| GND Pin Current | IGND | 15 | 25 | mA | VIN = VOUT(NOMINAL), ILOAD = 500mA (Note 6) | 3 | |
| EN/UV Pin Threshold (Turn-On, rising) | VEN/UV | 1.18 | 1.24 | 1.32 | V | VIN = 2V | 3 |
| EN/UV Pin Current | IEN | 8 | 15 | µA | VEN/UV = 1.24V, VIN = 20V | 4 | |
| EN/UV Pin Current | IEN | -1 | 1 | µA | VEN/UV = 20V, VIN = 0V | 4 | |
| Quiescent Current in Shutdown (E/I-Grade) | IQ(SHDN) | 0.3 | 1 | µA | VEN/UV = 0V, VIN = 6V, TJ ≤ 125°C (E/I-Grade) | 4 | |
| Internal Current Limit | ILIM | 570 | 710 | 850 | mA | VIN = 2V, VOUT = 0V | 4 |
| Programmable Current Limit | ILIM | 450 | 500 | 550 | mA | VIN = 2V, VOUT = 0V, RILIM = 300Ω | 4 |
| Programmable Current Limit | ILIM | 90 | 100 | 110 | mA | VIN = 2V, VOUT = 0V, RILIM = 1.5kΩ | 4 |
| PGFB Trip Point Rising | VPGFB | 291 | 300 | 309 | mV | PGFB Trip Point Rising | 4 |
| PG Output Low Voltage | VPG | 30 | 100 | mV | IPG = 100µA | 4 | |
| PG Leakage Current | IPG | 1 | µA | VPG = 20V | 4 | ||
| Reverse Input Current | IIN(REV) | 100 | µA | VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V | 4 | ||
| Reverse Output Current | IOUT(REV) | 14 | 25 | µA | VIN = 0, VOUT = 5V, SET = Open | 4 | |
| Minimum Load Required | ILOAD(MIN) | 10 | µA | VOUT < 1V | 4 | ||
| IN Pin Voltage | -22 | 22 | V | 2 | |||
| EN/UV Pin Voltage | -22 | 22 | V | 2 | |||
| IN-to-EN/UV Differential | -22 | 22 | V | 2 | |||
| PG Pin Voltage | -0.3 | 22 | V | Note 10 | 2 | ||
| ILIM Pin Voltage | -0.3 | 1 | V | Note 10 | 2 | ||
| PGFB Pin Voltage | -0.3 | 22 | V | Note 10 | 2 | ||
| SET Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| SET Pin Current | -20 | 20 | mA | Note 7 | 2 | ||
| OUTS Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| OUTS Pin Current | -20 | 20 | mA | Note 7 | 2 | ||
| OUT Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| OUT-to-OUTS Differential | -1.2 | 1.2 | V | Note 14 | 2 | ||
| IN-to-OUT Differential | -22 | 22 | V | 2 | |||
| IN-to-OUTS Differential | -22 | 22 | V | 2 | |||
| Operating Junction Temperature Range (I-Grade) | TJ | -40 | 125 | °C | I-Grade | 2 | |
| Maximum Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Thermal Resistance Junction-to-Ambient (DD package) | θJA | 34 | °C/W | DD (10-lead 3mm × 3mm DFN) package | 2 | ||
| Thermal Resistance Junction-to-Case (DD package) | θJC | 5.5 | °C/W | DD (10-lead 3mm × 3mm DFN) package | 2 | ||
| Thermal Resistance Junction-to-Ambient (DFN, measured) | θJA | 34 | 36 | °C/W | Table 3, 4-layer FR-4 board, copper area 2500mm² to 100mm² on topside | 22 |
CAD (KiCad official)
- Symbol:
LT3045IDD#PBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lt3045idd-pbf-etched.step/lt3045idd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3045idd-pbf.step/lt3045idd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
79a19c48f10093eb, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).