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LT3042MPDD#PBF

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Analog Devices Linear Voltage Regulators (LDO), DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslt3042mpdd#pbffactory-2.0.0extractor-text

Verified LT3042MPDD#PBF

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 11 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT3042MPDD#PBF · DFN-10-EP(3x3) · 11 pins
  • ✓copper: 11 copper pads, none touching another net
  • ✓datasheet: all 11 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C666570, digikey 505-LT3042MPDD#PBF-ND, mouser 584-LT3042MPDD#PBF
  • ✓family: DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-2r4tt9nu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 11 pins = 11 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 11 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt3042mpdd-pbf.kicad_sym✓ lt3042mpdd-pbf.kicad_mod✓ lt3042mpdd-pbf.step
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers lt3042mpdd-pbf: viewers · Ray 5d ago
lt3042mpdd-pbf-etched.glb Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf-etched.step lt3042mpdd-pbf: factory component page (tier=mfr) · Ray 5d ago
lt3042mpdd-pbf-hero.glb lt3042mpdd-pbf: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
lt3042mpdd-pbf-hero.overlay.json Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf.glb Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf.kicad_mod Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf.kicad_sym Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf.lbr Publish 0.1.0 · Ray 5d ago
lt3042mpdd-pbf.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 11 pins · Ray 5d ago

LT3042MPDD#PBF

Analog Devices · Linear Voltage Regulators (LDO) · DFN-10-EP(3x3)

LT3042MPDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Supplies power to the regulator and requires a bypass capacitor, with a minimum 4.7µF stated for stability; absolute maximum IN pin voltage is ±22V.
2 IN power_in Supplies power to the regulator in parallel with pin 1 and requires a bypass capacitor, with a minimum 4.7µF stated for stability; absolute maximum IN pin voltage is ±22V.
3 EN/UV input Pulling low places the part in shutdown; the turn-on threshold is 1.24V on a rising edge with 170mV hysteresis, and the pin must not float (tie to IN if unused).
4 PG output Open-collector power good flag that pulls low when PGFB is below 300mV; do not drive it more than 0.3V below GND.
5 ILIM passive Connecting a resistor to GND programs the current limit using a 125mA•kΩ scale factor; ILIM pin voltage is limited to -0.3V to 1V absolute maximum, and it should be tied to GND if unused.
6 PGFB input Power good feedback input where PG goes high when PGFB rises above 300mV with 7mV falling-edge hysteresis; absolute maximum PGFB pin voltage is -0.3V to 22V.
7 SET passive Sources a precision 100µA current through the external SET resistor so that VOUT = ISET • RSET over a 0V to 15V output range; absolute maximum SET pin voltage is -0.3V to 16V.
8 GND power_in Ground reference for the regulator, which must be tied directly to the exposed pad (pin 11) and soldered to the PCB ground.
9 OUTS input Output sense input to the noninverting input of the error amplifier that must be Kelvin connected to the output capacitor and load; absolute maximum OUTS pin voltage is -0.3V to 16V.
10 OUT power_out Supplies power to the load and requires a minimum 4.7µF output capacitor with ESR below 50mΩ and ESL below 2nH; absolute maximum OUT pin voltage is -0.3V to 16V.
11 GND power_in Exposed pad that is an electrical and thermal connection to GND and must be soldered to the PCB ground.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package DFN-10-EP(3x3)
Category Power Management ICs
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN Pin Voltage -22 22 V 2
EN/UV Pin Voltage -22 22 V 2
IN-to-EN/UV Differential -22 22 V 2
PG Pin Voltage -0.3 22 V Note 10 2
ILIM Pin Voltage -0.3 1 V Note 10 2
PGFB Pin Voltage -0.3 22 V Note 10 2
SET Pin Voltage -0.3 16 V Note 10 2
SET Pin Current -20 20 mA Note 7 2
OUTS Pin Voltage -0.3 16 V Note 10 2
OUTS Pin Current -20 20 mA Note 7 2
OUT Pin Voltage -0.3 16 V Note 10 2
OUT-to-OUTS Differential -1.2 1.2 V Note 14 2
IN-to-OUT Differential -22 22 V 2
IN-to-OUTS Differential -22 22 V 2
Operating Junction Temperature Range (MP-Grade) TJ -55 150 °C MP-Grade 2
Storage Temperature Range -65 150 °C 2
Junction-to-Ambient Thermal Resistance (DD package) θJA 34 °C/W DD package 2
Junction-to-Case Thermal Resistance (DD package) θJC 5.5 °C/W DD package 2
Minimum IN Pin Voltage 1.78 2 V ILOAD = 200mA, VIN UVLO Rising 3
VIN UVLO Hysteresis 75 mV 3
SET Pin Current (ISET) ISET 99 100 101 µA VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
SET Pin Current (ISET) over line and load ISET 98 100 102 µA 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Output Offset Voltage VOS (VOUT, VSET) VOS -1 1 mV VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
Output Offset Voltage VOS (VOUT, VSET) over line and load VOS -2 2 mV 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Line Regulation ΔISET ΔISET -2 0.5 2 nA/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V 3
Line Regulation ΔVOS ΔVOS -3 0.5 3 µV/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) 3
Load Regulation ΔVOS ΔVOS 0.1 0.5 mV ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V (Note 4) 3
Change in ISET with VSET (VSET 1.3V to 15V) ΔISET 30 150 nA VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET (VSET 1.3V to 15V) ΔVOS 0.03 0.3 mV VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) 3
Change in ISET with VSET (VSET 0V to 1.3V) ΔISET 400 600 nA VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET (VSET 0V to 1.3V) ΔVOS 0.6 2 mV VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) 3
Dropout Voltage 220 270 mV ILOAD = 1mA, 50mA 3
Dropout Voltage over temperature 300 mV ILOAD = 1mA, 50mA (full operating temperature range) 3
Dropout Voltage 270 mV ILOAD = 150mA (Note 5) 3
Dropout Voltage 350 mV ILOAD = 200mA (Note 5) 3
GND Pin Current IGND 1.9 mA VIN = VOUT(NOMINAL), ILOAD = 10µA (Note 6) 3
GND Pin Current IGND 2 3.5 mA VIN = VOUT(NOMINAL), ILOAD = 1mA (Note 6) 3
GND Pin Current IGND 3.2 5 mA VIN = VOUT(NOMINAL), ILOAD = 50mA (Note 6) 3
GND Pin Current IGND 4.5 7 mA VIN = VOUT(NOMINAL), ILOAD = 100mA (Note 6) 3
GND Pin Current IGND 7.6 13 mA VIN = VOUT(NOMINAL), ILOAD = 200mA (Note 6) 3
EN/UV Pin Threshold (Turn-On Rising) 1.18 1.24 1.32 V EN/UV Trip Point Rising (Turn-On), VIN = 2V 3
EN/UV Pin Hysteresis 170 mV EN/UV Trip Point Hysteresis, VIN = 2V 3
EN/UV Pin Current -1 0.2 1 µA VEN/UV = 0V, VIN = 20V 3
EN/UV Pin Current 8 15 µA VEN/UV = 1.24V, VIN = 20V 3
Quiescent Current in Shutdown 0.3 1 µA VEN/UV = 0V, VIN = 6V 4
Quiescent Current in Shutdown over temperature 10 µA VEN/UV = 0V, VIN = 6V (full operating temperature range) 4
Internal Current Limit 220 270 320 mA VIN = 2V, VOUT = 0V (Note 12) 4
Programmable Current Limit 180 200 220 mA VIN = 2V, VOUT = 0V, RILIM = 625Ω 4
Programmable Current Limit 45 50 55 mA VIN = 2V, VOUT = 0V, RILIM = 2.5kΩ 4
PGFB Trip Point Rising 291 300 309 mV PGFB Trip Point Rising 4
PGFB Hysteresis 7 mV PGFB Trip Point Hysteresis 4
PGFB Pin Current 25 nA VIN = 2V, VPGFB = 300mV 4
PG Output Low Voltage 30 100 mV IPG = 100µA 4
PG Leakage Current 1 µA VPG = 20V 4
Reverse Input Current 50 µA VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V 4
Reverse Output Current 2 5 µA VIN = 0, VOUT = 5V, SET = Open 4
Minimum Load Required 10 µA VOUT < 1V 4
Thermal Shutdown TJ Rising 162 °C TJ Rising 4
Thermal Shutdown Hysteresis 8 °C 4
Thermal Regulation -0.01 %/W 10ms Pulse 4

CAD (KiCad official)

  • Symbol: LT3042MPDD#PBF
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: lt3042mpdd-pbf-etched.step / lt3042mpdd-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3042mpdd-pbf.step / lt3042mpdd-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 c65c2b7406029d9b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF