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LT3042IMSE#PBF

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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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LT3042IMSE#PBF

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · MSOP-10-EP

LT3042IMSE#PBF from Analog Devices, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin; tie with pin 2 and bypass it, since a 4.7µF input capacitor generally suffices and the absolute maximum IN pin voltage is ±22V.
2 IN power_in Input supply pin; tie with pin 1 and bypass it, since a 4.7µF input capacitor generally suffices and the absolute maximum IN pin voltage is ±22V.
3 EN/UV input Enable/UVLO pin; pulling it low shuts the part down, it turns on above a 1.24V rising threshold with 170mV hysteresis, has a ±22V absolute maximum, and must not be left floating (tie to IN if unused).
4 PG output Open-collector power good flag that pulls low when PGFB is below 300mV, with a −0.3V to 22V absolute maximum and no more than 0.3V below GND in operation; float it if unused.
5 ILIM passive Current limit programming pin where a resistor to GND sets the limit using a 125mA·kΩ scale factor, with an absolute maximum range of −0.3V to 1V; tie it to GND if the function is not used.
6 PGFB input Power good feedback input where PG goes high when PGFB rises above 300mV (7mV falling hysteresis), with a −0.3V to 22V absolute maximum; tie it to IN if power good and fast start-up are not needed.
7 SET passive Error amplifier inverting input and 100µA set-point current source, where VOUT = ISET × RSET with output range 0V to 15V; the absolute maximum is −0.3V to 16V and ±20mA current.
8 GND power_in Ground pin that must be tied directly to the exposed backside pad and the PCB ground.
9 OUTS input Output sense input (noninverting error amplifier input) that should be Kelvin connected directly to the output capacitor and load; the absolute maximum is −0.3V to 16V and ±20mA current.
10 OUT power_out Output pin that supplies the load and needs a minimum 4.7µF ceramic output capacitor with ESR below 50mΩ and ESL below 2nH; the absolute maximum OUT voltage is −0.3V to 16V.
11 GND power_in Exposed pad that is an electrical GND connection, must be soldered to the PCB ground for proper electrical and thermal performance, and must be tied directly to the GND pin.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10-EP
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SET Pin Current (ISET), VIN = 2V, ILOAD = 1mA, VOUT = 1.3V ISET 99 100 101 µA VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
SET Pin Current (ISET), full range ISET 98 100 102 µA 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Output Offset Voltage VOS (VOUT, VSET) VOS -1 1 mV VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
Output Offset Voltage VOS (VOUT, VSET), full range VOS -2 2 mV 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3) 3
Line Regulation ∆ISET ∆ISET/∆VIN -2 0.5 2 nA/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V 3
Line Regulation ∆VOS ∆VOS/∆VIN -3 0.5 3 µV/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) 3
Load Regulation ∆VOS ∆VOS/∆ILOAD 0.1 0.5 mV ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V (Note 4) 3
Change in ISET with VSET ∆ISET 30 400 nA VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET ∆VOS 0.03 0.6 mV VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) 3
Change in ISET with VSET ∆ISET 150 600 nA VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET ∆VOS 0.3 2 mV VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) 3
Dropout Voltage 220 300 mV ILOAD = 1mA, 50mA 3
Dropout Voltage 270 mV ILOAD = 150mA (Note 5) 3
Dropout Voltage 350 mV ILOAD = 200mA (Note 5) 3
GND Pin Current IGND 2 3.5 mA VIN = VOUT(NOMINAL), ILOAD = 1mA (Note 6) 3
GND Pin Current IGND 3.2 5 mA VIN = VOUT(NOMINAL), ILOAD = 50mA (Note 6) 3
GND Pin Current IGND 4.5 7 mA VIN = VOUT(NOMINAL), ILOAD = 100mA (Note 6) 3
GND Pin Current IGND 7.6 13 mA VIN = VOUT(NOMINAL), ILOAD = 200mA (Note 6) 3
Minimum IN Pin Voltage 1.78 2 V ILOAD = 200mA, VIN UVLO Rising 3
EN/UV Pin Threshold, rising (turn-on) 1.18 1.24 1.32 V EN/UV Trip Point Rising (Turn-On), VIN = 2V 3
EN/UV Pin Current IEN -1 0.2 1 µA VEN/UV = 0V, VIN = 20V 3
EN/UV Pin Current IEN 8 15 µA VEN/UV = 1.24V, VIN = 20V 3
Quiescent Current in Shutdown IQ 0.3 1 µA VEN/UV = 0V, VIN = 6V 4
Quiescent Current in Shutdown IQ 10 µA VEN/UV = 0V, VIN = 6V 4
Internal Current Limit 220 270 320 mA VIN = 2V, VOUT = 0V 4
Internal Current Limit 130 180 250 mA VIN = 12V, VOUT = 0V 4
Programmable Current Limit ILIM 180 200 220 mA VIN = 2V, VOUT = 0V, RILIM = 625Ω 4
Programmable Current Limit ILIM 45 50 55 mA VIN = 2V, VOUT = 0V, RILIM = 2.5kΩ 4
PGFB Trip Point Rising VPGFB 291 300 309 mV PGFB Trip Point Rising 4
PG Output Low Voltage VPG 30 100 mV IPG = 100µA 4
PG Leakage Current IPG 1 µA VPG = 20V 4
Reverse Input Current IIN 50 µA VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V 4
Reverse Output Current IOUT 2 5 µA VIN = 0, VOUT = 5V, SET = Open 4
Minimum Load Required ILOAD 10 µA VOUT < 1V 4
IN Pin Voltage -22 22 V 2
EN/UV Pin Voltage -22 22 V 2
IN-to-EN/UV Differential -22 22 V 2
PG Pin Voltage -0.3 22 V Note 10 2
ILIM Pin Voltage -0.3 1 V Note 10 2
PGFB Pin Voltage -0.3 22 V Note 10 2
SET Pin Voltage -0.3 16 V Note 10 2
SET Pin Current -20 20 mA Note 7 2
OUTS Pin Voltage -0.3 16 V Note 10 2
OUTS Pin Current -20 20 mA Note 7 2
OUT Pin Voltage -0.3 16 V Note 10 2
OUT-to-OUTS Differential -1.2 1.2 V Note 14 2
IN-to-OUT Differential -22 22 V 2
IN-to-OUTS Differential -22 22 V 2
Operating Junction Temperature Range, I-Grade TJ -40 125 °C E-, I-Grade (Note 9) 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature (Soldering, 10 Sec) 300 °C MSE Package 2
Maximum Junction Temperature TJMAX 150 °C MSE Package 2
Thermal Resistance, junction to ambient θJA 33 °C/W MSE Package 2
Thermal Resistance, junction to case θJC 8 °C/W MSE Package 2

CAD (KiCad official)

  • Symbol: LT3042IMSE#PBF
  • Footprint: Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm
  • 3D model: MSOP-10-EP (KiCad packages3D, STEP)
  • 3D model files: lt3042imse-pbf-etched.step / lt3042imse-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3042imse-pbf.step / lt3042imse-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 c65c2b7406029d9b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF