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LT3042HDD#TRPBF

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Analog Devices Linear Voltage Regulators (LDO), TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslt3042hdd#trpbffactory-2.0.0extractor-text

Verified LT3042HDD#TRPBF

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 11 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT3042HDD#TRPBF · TDFN-10-EP(3x3) · 11 pins
  • ✓copper: 11 copper pads, none touching another net
  • ✓datasheet: all 11 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C666564, digikey LT3042HDD#TRPBFTR-ND, mouser 584-LT3042HDD#TRPBF
  • ✓family: DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1jodbmsc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.29)
  • ✓pads: 11 pins = 11 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 11 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt3042hdd-trpbf.kicad_sym✓ lt3042hdd-trpbf.kicad_mod✓ lt3042hdd-trpbf.step
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers lt3042hdd-trpbf: viewers · Ray 7d ago
lt3042hdd-trpbf-etched.glb Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf-etched.step lt3042hdd-trpbf: factory component page (tier=mfr) · Ray 7d ago
lt3042hdd-trpbf-hero.glb lt3042hdd-trpbf: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
lt3042hdd-trpbf-hero.overlay.json Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf.glb Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf.kicad_mod Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf.kicad_sym Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf.lbr Publish 0.1.0 · Ray 7d ago
lt3042hdd-trpbf.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago
verification.json Verified: Published by the parts factory: tier mfr, 11 pins · Ray 7d ago

LT3042HDD#TRPBF

Analog Devices · Linear Voltage Regulators (LDO) · TDFN-10-EP(3x3)

LT3042HDD#TRPBF from Analog Devices, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin (shared with pin 2) requiring a bypass capacitor, typically 4.7µF; withstands reverse voltages with respect to GND, OUTS and OUT, and absolute maximum is ±22V.
2 IN power_in Input supply pin (shared with pin 1) requiring a bypass capacitor, typically 4.7µF; withstands reverse voltages with respect to GND, OUTS and OUT, and absolute maximum is ±22V.
3 EN/UV input Enable/UVLO pin that turns on above 1.24V rising with 170mV hysteresis, shuts down below that with <1µA quiescent current, can set a UVLO via resistor divider, and must be tied to IN if unused, never floated.
4 PG output Open-collector power good flag that pulls low if PGFB is below 300mV; float if unused and do not drive more than 0.3V below GND.
5 ILIM passive Current limit programming pin where a resistor to GND sets the limit with a 125mA•kΩ scale factor, sources current proportional (1:400) to output current with 0V to 300mV monitoring range, and is tied to GND if unused.
6 PGFB input Power good feedback input with 300mV rising threshold and 7mV hysteresis, set by a divider from OUT, also enables fast start-up circuitry; tie to IN if power good and fast start-up are not needed.
7 SET passive Error amplifier inverting input and regulation set-point that sources a precision 100µA through an external resistor to GND (VSET = ISET•RSET), output range 0V to 15V, with an optional capacitor to GND for noise and PSRR.
8 GND power_in Ground pin, tied directly to the exposed pad, which must be soldered to PCB ground for electrical and thermal performance.
9 OUTS input Output sense pin, the noninverting input to the error amplifier, Kelvin connected directly to the output capacitor and load; do not drive more than 0.3V below GND.
10 OUT power_out Regulated output supplying up to 200mA to the load, requiring a minimum 4.7µF output capacitor with ESR below 50mΩ and ESL below 2nH; absolute maximum is 16V.
11 GND power_in Exposed pad is an electrical connection to GND and must be soldered to the PCB ground and tied directly to the GND pin.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TDFN-10-EP(3x3)
Category Power Management ICs
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SET Pin Current ISET 99 100 101 µA VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
SET Pin Current ISET 98 100 102 µA 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA 3
Output Offset Voltage VOS -1 1 mV VIN = 2V, ILOAD = 1mA, VOUT = 1.3V 3
Output Offset Voltage VOS -2 2 mV 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA 3
Minimum IN Pin Voltage VIN(MIN) 1.78 2 V ILOAD = 200mA, VIN UVLO Rising 3
Line Regulation ISET ΔISET -2 0.5 2 nA/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V 3
Line Regulation VOS ΔVOS -3 0.5 3 µV/V VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V 3
Load Regulation VOS ΔVOS 0.1 0.5 mV ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V 3
Change in ISET with VSET 30 400 nA VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET 0.03 0.6 mV VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA 3
Change in ISET with VSET 150 600 nA VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA 3
Change in VOS with VSET 0.3 2 mV VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA 3
Dropout Voltage 220 270 mV ILOAD = 1mA, 50mA 3
GND Pin Current IGND 2 3.5 mA ILOAD = 1mA, VIN = VOUT(NOMINAL) 3
GND Pin Current IGND 3.2 5 mA ILOAD = 50mA, VIN = VOUT(NOMINAL) 3
GND Pin Current IGND 4.5 7 mA ILOAD = 100mA, VIN = VOUT(NOMINAL) 3
GND Pin Current IGND 7.6 13 mA ILOAD = 200mA, VIN = VOUT(NOMINAL) 3
EN/UV Pin Threshold 1.18 1.24 1.32 V EN/UV Trip Point Rising (Turn-On), VIN = 2V 3
Quiescent Current in Shutdown 0.3 10 µA VEN/UV = 0V, VIN = 6V 4
Internal Current Limit 220 270 320 mA VIN = 2V, VOUT = 0V 4
Internal Current Limit 300 mA VIN = 12V, VOUT = 0V 4
Internal Current Limit 130 180 250 mA VIN = 20V, VOUT = 0V 4
Programmable Current Limit 180 200 220 mA VIN = 2V, VOUT = 0V, RILIM = 625Ω 4
Programmable Current Limit 45 50 55 mA VIN = 2V, VOUT = 0V, RILIM = 2.5kΩ 4
PGFB Trip Point 291 300 309 mV PGFB Trip Point Rising 4
PG Output Low Voltage 30 100 mV IPG = 100µA 4
PG Leakage Current 1 µA VPG = 20V 4
Reverse Input Current 50 µA VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V 4
Reverse Output Current 2 5 µA VIN = 0, VOUT = 5V, SET = Open 4
Minimum Load Required 10 µA VOUT < 1V 4
Current Limit Programming Scale Factor 125 mA•kΩ 2V< VIN < 20V 4
Fast Start-Up Set Pin Current 2 mA VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V 3
Load Regulation ISET ΔISET 3 nA ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V 3
Dropout Voltage 270 mV ILOAD = 150mA 3
Dropout Voltage 350 mV ILOAD = 200mA 3
GND Pin Current IGND 1.9 mA ILOAD = 10µA, VIN = VOUT(NOMINAL) 3
EN/UV Pin Hysteresis 170 mV EN/UV Trip Point Hysteresis, VIN = 2V 3
PGFB Hysteresis 7 mV PGFB Trip Point Hysteresis 4
Thermal Shutdown 162 °C TJ Rising 4
Thermal Shutdown Hysteresis 8 °C 4
Output RMS Noise 0.8 µVRMS ILOAD = 200mA, BW = 10Hz to 100kHz, COUT = 4.7µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V 3
Ripple Rejection PSRR 117 dB VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 200mA, COUT = 4.7µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V 3
Start-Up Time 55 ms VOUT(NOM) = 5V, ILOAD = 200mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V 4
Start-Up Time 550 ms VOUT(NOM) = 5V, ILOAD = 200mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V 4
Thermal Regulation -0.01 %/W 10ms Pulse 4
IN Pin Voltage -22 22 V 2
EN/UV Pin Voltage -22 22 V 2
IN-to-EN/UV Differential -22 22 V 2
PG Pin Voltage -0.3 22 V 2
ILIM Pin Voltage -0.3 1 V 2
PGFB Pin Voltage -0.3 22 V 2
SET Pin Voltage -0.3 16 V 2
SET Pin Current -20 20 mA 2
OUTS Pin Voltage -0.3 16 V 2
OUTS Pin Current -20 20 mA 2
OUT Pin Voltage -0.3 16 V 2
OUT-to-OUTS Differential -1.2 1.2 V 2
IN-to-OUT Differential -22 22 V 2
IN-to-OUTS Differential -22 22 V 2
Operating Junction Temperature Range, H-Grade TJ -40 150 °C H-Grade 2
Storage Temperature Range TSTG -65 150 °C 2
Junction-to-Ambient Thermal Resistance θJA 34 °C/W DD package, TJMAX = 150°C 2
Junction-to-Case Thermal Resistance θJC 5.5 °C/W DD package 2

CAD (KiCad official)

  • Symbol: LT3042HDD#TRPBF
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: lt3042hdd-trpbf-etched.step / lt3042hdd-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3042hdd-trpbf.step / lt3042hdd-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 c65c2b7406029d9b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF