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LT3029EDE#PBF

Analog Devices · Linear Voltage Regulators (LDO) · DFN-16-EP(3x4)

LT3029EDE#PBF from Analog Devices, in a DFN-16-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BYP1 passive Bypass pin for the channel 1 reference, clamped to ±0.6V from ground, where a maximum 10nF capacitor from OUT1 reduces output noise to a typical 20µVRMS over 10Hz to 100kHz.
2 NC unconnected No connect pin that is not tied to any internal circuitry and may be floated, tied to VIN or tied to GND.
3 OUT1 power_out Channel 1 regulator output supplying up to 500mA, which requires a minimum 3.3µF output capacitor to prevent oscillation.
4 OUT1 power_out Channel 1 regulator output supplying up to 500mA, which requires a minimum 3.3µF output capacitor to prevent oscillation.
5 GND power_in Ground pin that must be tied directly to the exposed pad (pin 17) and to the bottom of the output voltage setting resistor divider for optimum load regulation.
6 OUT2 power_out Channel 2 regulator output supplying up to 500mA, which requires a minimum 3.3µF output capacitor to prevent oscillation.
7 OUT2 power_out Channel 2 regulator output supplying up to 500mA, which requires a minimum 3.3µF output capacitor to prevent oscillation.
8 BYP2 passive Bypass pin for the channel 2 reference, clamped to ±0.6V from ground, where a maximum 10nF capacitor from OUT2 reduces output noise to a typical 20µVRMS over 10Hz to 100kHz.
9 ADJ2 input Channel 2 adjust pin, the error amplifier input held at 1.215V referenced to ground, clamped to ±9V, with a typical 30nA bias current, giving an output range of 1.215V to 19.5V.
10 SHDN2 input Channel 2 shutdown pin where pulling it low turns the channel 2 output off, and it may be left unconnected only as the datasheet describes, with shutdown pin current typically less than 1µA.
11 IN2 power_in Channel 2 input supply pin that powers channel 2 over an input range of 1.8V to 20V and may need a 1µF to 10µF bypass capacitor when far from the main input filter.
12 IN2 power_in Channel 2 input supply pin that powers channel 2 over an input range of 1.8V to 20V and may need a 1µF to 10µF bypass capacitor when far from the main input filter.
13 IN1 power_in Channel 1 input supply pin that powers channel 1 over an input range of 1.8V to 20V and may need a 1µF to 10µF bypass capacitor when far from the main input filter.
14 IN1 power_in Channel 1 input supply pin that powers channel 1 over an input range of 1.8V to 20V and may need a 1µF to 10µF bypass capacitor when far from the main input filter.
15 SHDN1 input Channel 1 shutdown pin where pulling it low turns the channel 1 output off, with shutdown pin current typically less than 1µA.
16 ADJ1 input Channel 1 adjust pin, the error amplifier input held at 1.215V referenced to ground, clamped to ±9V, with a typical 30nA bias current, giving an output range of 1.215V to 19.5V.
17 GND power_in Exposed pad that is the electrical and thermal GND connection and must be soldered to PCB ground and tied directly to pin 5.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package DFN-16-EP(3x4)
Category Power Management ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN1, IN2 Pin Voltage -22 22 V 2
OUT1, OUT2 Pin Voltage -22 22 V 2
Input-to-Output Differential Voltage -22 22 V 2
ADJ1, ADJ2 Pin Voltage -9 9 V 2
BYP1, BYP2 Pin Voltage -0.6 0.6 V 2
SHDN1, SHDN2 Pin Voltage -22 22 V 2
Operating Junction Temperature (LT3029E) TJ -40 125 °C LT3029E 2
Storage Temperature Range -65 150 °C 2
ADJ1, ADJ2 Pin Voltage 1.203 1.215 1.227 V VIN = 2V, ILOAD = 1mA 3
ADJ1, ADJ2 Pin Voltage 1.191 1.215 1.239 V 2.3V < VIN < 20V, 1mA < ILOAD < 500mA (E, I, MP) 3
Shutdown Threshold (Off to On) 0.45 1.1 V VOUT = Off to On 3
Shutdown Threshold (On to Off) 0.2 0.4 V VOUT = On to Off 3
Ripple Rejection 55 67 dB VIN = 2.715V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 500mA 3
Current Limit 520 mA VIN = 2.3V, ∆VOUT = -0.1V 3
Input Reverse Leakage Current 1 mA VIN = -20V, VOUT = 0V 3
Load Regulation (E, I, MP) 15 mV VIN = 2.3V, ∆ILOAD = 1mA to 500mA (E, I, MP) 3
Load Regulation 2.5 6 mV VIN = 2.3V, ∆ILOAD = 1mA to 500mA 3
Line Regulation 0.5 5 mV ∆VIN = 2V to 20V, ILOAD = 1mA 3
Minimum Input Voltage 1.8 2.3 V ILOAD = 500mA 3
Dropout Voltage 0.11 0.18 V VIN = VOUT(NOMINAL), ILOAD = 10mA 3
Dropout Voltage 0.25 V VIN = VOUT(NOMINAL), ILOAD = 10mA, over full operating temperature range 3
Dropout Voltage 0.16 0.22 V VIN = VOUT(NOMINAL), ILOAD = 50mA 3
Dropout Voltage 0.31 V VIN = VOUT(NOMINAL), ILOAD = 50mA, over full operating temperature range 3
Dropout Voltage 0.2 0.25 V VIN = VOUT(NOMINAL), ILOAD = 100mA 3
Dropout Voltage 0.34 V VIN = VOUT(NOMINAL), ILOAD = 100mA, over full operating temperature range 3
Dropout Voltage 0.3 0.36 V VIN = VOUT(NOMINAL), ILOAD = 500mA 3
Dropout Voltage 0.46 V VIN = VOUT(NOMINAL), ILOAD = 500mA, over full operating temperature range 3
GND Pin Current (per Channel) 55 150 µA VIN = VOUT(NOMINAL), ILOAD = 0mA 3
GND Pin Current (per Channel) 90 250 µA VIN = VOUT(NOMINAL), ILOAD = 1mA 3
GND Pin Current (per Channel) 1.1 2 mA VIN = VOUT(NOMINAL), ILOAD = 50mA 3
GND Pin Current (per Channel) 2 3.5 mA VIN = VOUT(NOMINAL), ILOAD = 100mA 3
GND Pin Current (per Channel) 4.3 8 mA VIN = VOUT(NOMINAL), ILOAD = 250mA 3
GND Pin Current (per Channel) 10 16 mA VIN = VOUT(NOMINAL), ILOAD = 500mA 3
ADJ1/ADJ2 Pin Bias Current 30 100 nA ADJ1, ADJ2 3
SHDN1/SHDN2 Pin Current 0 0.5 µA VSHDN1, VSHDN2 = 0V 3
SHDN1/SHDN2 Pin Current 0.6 3 µA VSHDN1, VSHDN2 = 20V 3
Quiescent Current in Shutdown (per Channel) 0.01 0.1 µA VIN = 6V, VSHDN1 = 0V, VSHDN2 = 0V 3
Current Limit 1.5 A VIN = 7V, VOUT = 0V 3
Reverse Output Current 0.5 10 µA VOUT = 1.215V, VIN = 0V 3
Output Voltage Noise 20 µVRMS COUT = 10µF, CBYP = 10nF, ILOAD = 500mA, BW = 10Hz to 100kHz 3
Thermal Resistance, Junction-to-Ambient θJA 38 °C/W DE package (16-lead 4mm × 3mm DFN) 2
Thermal Resistance, Junction-to-Case θJC 4.3 °C/W DE package (16-lead 4mm × 3mm DFN), measured at exposed pad 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts COPPER Table 2. DE Package, 16-Lead DFN COPPER AREA THERMAL RESISTANCE 15

CAD (KiCad official)

  • Symbol: LT3029EDE#PBF
  • Footprint: Package_DFN_QFN:DFN-16-1EP_3x4mm_P0.45mm_EP1.7x3.3mm
  • 3D model: DFN-16-EP(3x4) (KiCad packages3D, STEP)
  • 3D model files: lt3029ede-pbf-etched.step / lt3029ede-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3029ede-pbf.step / lt3029ede-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 08d182f1012f90a4, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF