LT1970ACFE#PBF from Analog Devices, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VEE	power_in	Minus supply voltage connected to the die substrate, which must always be the most negative voltage applied to the part and may be negative or ground; any or all VEE pins may be used and unused ones must remain open.
2	V-	power_in	Output stage negative supply that may equal VEE or be smaller in magnitude, carries only output stage current, can drive the base/gate of an external boost device, and should otherwise be decoupled to ground with a low ESR capacitor.
3	OUT	output	Amplifier output and force connection of a Kelvin sensed load, normally tied to the external current sense resistor and SENSE+, and current limited to ±800mA typical.
4	SENSE+	input	Positive current sense pin normally connected to the driven end of the external sense resistor; sourcing limit activates when VSENSE equals 1/10 of the VCSRC voltage and sinking limit when VSENSE equals -1/10 of the VCSNK voltage.
5	FILTER	passive	Current sense filter pin normally left open or shorted to SENSE-, which can adapt the current sense response time with a 1nF to 100nF capacitor to SENSE- working with an internal 1k resistor.
6	SENSE-	input	Negative current sense pin normally connected to the load end of the external sense resistor, with current limiting activating at VSENSE equal to 1/10 of VCSRC (sourcing) or -1/10 of VCSNK (sinking).
7	VCC	power_in	Positive supply voltage for all circuitry except the output transistors, with total VCC to VEE supply between 3.5V and 36V, VCC always greater than or equal to V+, and decoupled to ground with a low ESR capacitor.
8	-IN	input	Inverting amplifier input that may be any voltage from VEE - 0.3V to VEE + 36V and stays high impedance at all times, and must never go below VEE - 0.3V even transiently.
9	+IN	input	Noninverting amplifier input that may be any voltage from VEE - 0.3V to VEE + 36V and stays high impedance at all times, and must never go below VEE - 0.3V even transiently.
10	VEE	power_in	Minus supply voltage connected to the die substrate, which must always be the most negative voltage applied to the part; any or all VEE pins may be used and unused ones must remain open.
11	VEE	power_in	Minus supply voltage connected to the die substrate, which must always be the most negative voltage applied to the part; any or all VEE pins may be used and unused ones must remain open.
12	VCSNK	input	Sink current limit control voltage input that sets the sink limit at a sense voltage of -1.0 • VVCSNK/10, may be set between VCOMMON and VCOMMON + 6V, and is linear except below 60mV with a typical 4mV minimum VSENSE set point.
13	VCSRC	input	Source current limit control voltage input that sets the source limit at a sense voltage of VVCSRC/10, may be set between VCOMMON and VCOMMON + 6V, and is linear except below 60mV with a typical 4mV minimum VSENSE set point.
14	COMMON	passive	Reference pin for the control and ENABLE inputs and flag outputs, which may be at any potential between VEE and VCC - 3V and is normally connected to ground.
15	ENABLE	input	TTL-level digital enable input that turns off the amplifier output and drops supply current to less than 1mA when taken low, and can be used to force zero output current.
16	ISRC	output	Open-collector sourcing current limit flag that pulls low whenever the sourcing current limit amplifier controls the output, sinks up to 10mA, may be wire-ORed with ISNK and TSD, and may be left open if unused.
17	ISNK	output	Open-collector sinking current limit flag that pulls low whenever the sinking current limit amplifier controls the output, sinks up to 10mA, may be wire-ORed with ISRC and TSD, and may be left open if unused.
18	TSD	output	Open-collector thermal shutdown flag that pulls low when the internal thermal shutdown activates at a typical die temperature of 160°C, sinks up to 10mA, may be wire-ORed with ISRC and ISNK, and may be left open if unused.
19	V+	power_in	Output stage positive supply that may equal VCC or be smaller in magnitude, carries only output stage current, can drive the base/gate of an external boost device, and should otherwise be decoupled to ground with a low ESR capacitor.
20	VEE	power_in	Minus supply voltage connected to the die substrate, which must always be the most negative voltage applied to the part; any or all VEE pins may be used and unused ones must remain open.
21	Exposed Pad	power_in	Exposed backside of the package electrically connected to the VEE pins on the die, to be soldered to a heat spreading PC board pad that is electrically connected to VEE.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20-EP
Category	Operational Amplifier/Comparator
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VCC to VEE)				36	V		2
Input Current				10	mA		2
Maximum Junction Temperature	TJMAX			150	°C		2
Storage Temperature Range		-65		150	°C		2
Lead Temperature (Soldering, 10 sec)				300	°C		2
Operating Temperature Range		-40		85	°C	Note 2	2
Specified Temperature Range LT1970AC		0		70	°C		2
Total Supply Voltage	VCC to VEE	3.5		36	V	Pin function description (page 1 states 5V to 36V)	8
Thermal Resistance Junction-to-Ambient	θJA		40		°C/W	Note 8, exposed pad soldered to PCB	2
Input Offset Voltage	VOS		200	600	µV	TA = 25°C	2
Input Offset Voltage	VOS			1000	µV	0°C < TA < 70°C	2
Input Offset Voltage Drift		-10	-4	10	µV/°C	Note 4	2
Input Offset Current	IOS	-100		100	nA	VCM = 0V	2
Input Bias Current	IB	-600	-160		nA	VCM = 0V	2
Input Voltage Range, Guaranteed by CMRR Test	VCM	-12		12	V	Guaranteed by CMRR Test	3
Common Mode Rejection Ratio	CMRR	92	105		dB	-12V < VCM < 12V	3
Power Supply Rejection Ratio	PSRR	90	100		dB	VEE = V- = -5V, VCC = V+ = 3V to 30V	3
Power Supply Rejection Ratio	PSRR	110	130		dB	VEE = V- = -5V, VCC = 30V, V+ = 2.5V to 30V	3
Large-Signal Voltage Gain	AVOL	100	150		V/mV	RL = 1k, -12.5V < VOUT < 12.5V	3
Large-Signal Voltage Gain	AVOL	80	120		V/mV	RL = 100Ω, -12.5V < VOUT < 12.5V	3
Large-Signal Voltage Gain	AVOL	20	45		V/mV	RL = 10Ω, -5V < VOUT < 5V, V+ = -V- = 8V	3
Output Sat Voltage Low	VOL		1.9	2.5	V	VOL = VOUT, V-, RL = 100, VCC = V+ = 15V, VEE = V- = -15V	3
Output Sat Voltage High	VOH		1.7	2.3	V	VOH = V+, VOUT, RL = 100, VCC = V+ = 15V, VEE = V- = -15V	3
Output Short-Circuit Current Output Low	ISC	500	800	1200	mA	Output Low, RSENSE = 0Ω	3
Output Short-Circuit Current Output High	ISC	-1000	-800	-500	mA	Output High, RSENSE = 0Ω	3
Slew Rate	SR	0.7	1.6		V/µs	-10V < VOUT < 10V, RL = 1k	3
Minimum Current Sense Voltage	VSENSE(MIN)	0.1	4	7	mV	VCSRC = VCSNK = 0V	3
Current Sense Voltage 4% of Full Scale	VSENSE(4%)	15	20	25	mV	VCSRC = VCSNK = 0.2V	3
Current Sense Voltage 10% of Full Scale	VSENSE(10%)	45	50	55	mV	VCSRC = VCSNK = 0.5V	3
Current Sense Voltage 100% of Full Scale	VSENSE(FS)	495	500	505	mV	VCSRC = VCSNK = 5V	3
Current Limit Control Input Bias Current	IBI	-1	-0.2	0.1	µA		3
SENSE- Input Current	ISENSE-	-500		500	nA	0V < (VCSRC, VCSNK) < 5V	3
FILTER Input Current	IFILTER	-500		500	nA	0V < (VCSRC, VCSNK) < 5V	3
SENSE+ Input Current	ISENSE+	-500		500	nA	VCSRC= VCSNK = 0V	3
SENSE+ Input Current	ISENSE+	200	250	300	µA	VCSRC = 5V, VCSNK = 0V	3
SENSE+ Input Current	ISENSE+	-300	-250	-200	µA	VCSRC= 0V, VCSNK = 5V	3
SENSE+ Input Current	ISENSE+	-25		25	µA	VCSRC = VCSNK = 5V	3
Resistance FILTER to SENSE-	RCSF	750	1000	1250	Ω		4
Logic Output Leakage ISRC, ISNK, TSD				1	µA	V = 15V	4
Logic Low Output Level			0.2	0.4	V	I = 5mA (Note 6)	4
Enable Logic Threshold	VENABLE	0.8	1.9	2.5	V		4
Enable Pin Bias Current	IENABLE	-1		1	µA		4
Total Supply Current	ISUPPLY		7	13	mA	VCC, V+ and V-, VEE Connected	4
VCC Supply Current	ICC		3	7	mA	VCC, V+ and V-, VEE Separate	4
Supply Current Disabled	ICC(STBY)		0.6	1.5	mA	VCC, V+ and V-, VEE Connected, VENABLE ≤ 0.8V	4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		The LT1970A is packaged in a 20-lead TSSOP package with a thermally conductive copper bottom plate to help	1

CAD (KiCad official)

Symbol: LT1970ACFE#PBF
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: lt1970acfe-pbf-etched.step / lt1970acfe-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1970acfe-pbf.step / lt1970acfe-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 0c1660be2dc25164, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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LT1970ACFE#PBF

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