component

LT1671CS8#PBF

Public Made by Adom

by adom

Analog Devices Pre-ordered Chips, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icslt1671cs8#pbffactory-2.0.0extractor-text

Verified LT1671CS8#PBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT1671CS8#PBF · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 12-page datasheet
  • ✓distributor: lcsc C664561, digikey LT1671CS8#PBF-ND, mouser 584-LT1671CS8#PBF
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-iivcettr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt1671cs8-pbf.kicad_sym✓ lt1671cs8-pbf.kicad_mod✓ lt1671cs8-pbf.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers lt1671cs8-pbf: viewers · Ray 10d ago
lt1671cs8-pbf-etched.glb Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf-etched.step lt1671cs8-pbf: factory component page (tier=mfr) · Ray 10d ago
lt1671cs8-pbf-hero.glb lt1671cs8-pbf: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
lt1671cs8-pbf-hero.overlay.json Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf.glb Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf.kicad_mod Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf.kicad_sym Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf.lbr Publish 0.1.0 · Ray 10d ago
lt1671cs8-pbf.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago

LT1671CS8#PBF

Analog Devices · Pre-ordered Chips · SO-8

LT1671CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive supply voltage, normally 5V.
2 +IN input Noninverting comparator input; inputs can exceed the supplies without phase reversal.
3 -IN input Inverting comparator input; the input common mode range extends from 1.5V below the positive supply down to the negative supply rail.
4 V- power_in Negative supply voltage, normally either 0V or -5V.
5 LATCH ENABLE input Latch control pin; when high, the outputs remain latched independent of the current state of the inputs, and the pin has no built-in hysteresis.
6 GND power_in Ground.
7 Q OUT output Noninverting logic output, high when +IN is above -IN and LATCH ENABLE is low.
8 Q OUT output Inverting logic output, low when +IN is above -IN and LATCH ENABLE is low.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Total Supply Voltage (V+ to V-) 12 V 2
Positive Supply Voltage 7 V 2
Negative Supply Voltage -7 V 2
Differential Input Voltage -12 12 V 2
Input and Latch Current -10 10 mA Note 2 2
Output Current (Continuous) -20 20 mA Note 2 2
Operating Temperature Range -40 85 °C 2
Specified Temperature Range -40 85 °C Note 3 2
Junction Temperature TJMAX 150 °C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature 300 °C Soldering, 10 sec. 2
Thermal Resistance Junction to Ambient θJA 190 °C/W S8 package 2
Input Offset Voltage VOS 0.8 2.5 mV RS ≤ 100Ω (Note 4) 2
Input Offset Voltage over temperature VOS 4 mV ● over full operating temperature range; RS ≤ 100Ω (Note 4) 2
Input Offset Voltage Drift ∆VOS/∆T 4 µV/°C ● over full operating temperature range 2
Input Offset Current IOS 10 100 nA 2
Input Offset Current over temperature IOS 150 nA ● 2
Input Bias Current IB 120 280 nA Note 5 2
Input Bias Current over temperature IB 350 nA ●, Note 5 2
Input Voltage Range VCMR -5 3.5 V ● Note 6 2
Input Voltage Range, Single 5V Supply VCMR 0 3.5 V ● Single 5V Supply 2
Common Mode Rejection Ratio CMRR 55 100 dB -5V ≤ VCM ≤ 3.5V, TA > 0°C 2
Common Mode Rejection Ratio CMRR 55 dB -5V ≤ VCM ≤ 3.3V, TA ≤ 0°C; Single 5V Supply row 2
Power Supply Rejection Ratio PSRR 50 85 dB ● 4.6V ≤ V+ ≤ 5.4V 2
Power Supply Rejection Ratio PSRR 60 90 dB ● -7V ≤ V- ≤ -2V 2
Small Signal Voltage Gain AV 2500 5000 V/V 1V ≤ VOUT ≤ 2V 2
Output Voltage Swing High VOH 2.7 3.1 V ● V+ ≥ 4.6V, IOUT = 400µA 3
Output Voltage Swing High VOH 2.4 3 V V+ ≥ 4.6V, IOUT = 4mA 3
Output Voltage Swing Low VOL 0.3 0.5 V ● IOUT = -400µA 3
Output Voltage Swing Low VOL 0.4 V IOUT = -4mA 3
Positive Supply Current I+ 450 800 µA 3
Positive Supply Current over temperature I+ 1000 µA ● 3
Negative Supply Current I- 75 200 µA 3
Negative Supply Current over temperature I- 250 µA ● 3
LATCH Pin High Input Voltage VIH 2 V ● 3
LATCH Pin Low Input Voltage VIL 0.8 V ● 3
LATCH Pin Current IIL -1000 -250 nA ● VLATCH = 0V 3
Propagation Delay tPD1 60 80 ns ∆VIN = 100mV, VOD = 20mV 3
Propagation Delay over temperature tPD1 110 ns ● ∆VIN = 100mV, VOD = 20mV 3
Propagation Delay (Note 7) tPD2 85 100 ns ∆VIN = 100mV, VOD = 5mV 3
Propagation Delay over temperature (Note 7) tPD2 130 ns ● ∆VIN = 100mV, VOD = 5mV 3
Differential Propagation Delay (Note 7) ∆tPD 15 30 ns ∆VIN = 100mV, VOD = 5mV 3
Minimum Disable Pulse Width tPW(D) 30 ns 3

CAD (KiCad official)

  • Symbol: LT1671CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1671cs8-pbf-etched.step / lt1671cs8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1671cs8-pbf.step / lt1671cs8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 4e3bb61bd867e99c, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF