component

LT1641-1CS8#PBF

Public Made by Adom

by adom

Analog Devices Surge Suppressors, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttvs-fuse-board level protectionlt1641-1cs8#pbffactory-2.0.0extractor-text

Verified LT1641-1CS8#PBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT1641-1CS8#PBF · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 12-page datasheet
  • ✓distributor: lcsc C664550, digikey LT1641-1CS8#PBF-ND, mouser 584-LT1641-1CS8#PBF
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 6 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0v3q4vxi/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 1 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.12)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 1 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt1641-1cs8-pbf.kicad_sym✓ lt1641-1cs8-pbf.kicad_mod✓ lt1641-1cs8-pbf.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs lt1641-1cs8-pbf: hero re-rendered with the chip (after the 10-30 render outage) · Ray 10d ago
viewers lt1641-1cs8-pbf: viewers · Ray 10d ago
lt1641-1cs8-pbf-hero.glb Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf-hero.overlay.json Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf.glb Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf.kicad_mod Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf.kicad_sym Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf.lbr Publish 0.1.0 · Ray 10d ago
lt1641-1cs8-pbf.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 10d ago

LT1641-1CS8#PBF

Analog Devices · Surge Suppressors · SO-8

LT1641-1CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ON input Undervoltage lockout input: GATE is pulled low when ON falls below the 1.233V threshold and turns back on above 1.313V, and pulsing ON low resets a latched current-limit fault.
2 FB input Power-good comparator input that monitors the output voltage through an external divider; PWRGD goes low below 1.233V and releases above 1.313V, and FB also sets the foldback current limit.
3 PWRGD output Open-collector power-good output to GND that is pulled low when FB is below 1.233V and goes high impedance above 1.313V, with an external pull-up that can be as high as 100V.
4 GND power_in Chip ground reference for the controller.
5 TIMER passive Timing input where an external capacitor sets the maximum time in current limit; at 1.233V the GATE is pulled low, and the timing capacitor must be at least 1.5nF.
6 GATE output High-side gate drive for the external N-channel MOSFET that guarantees at least 10V gate drive above 20V VCC and 4.5V between 10.8V and 20V, and is pulled to GND on faults.
7 SENSE input Current-limit sense input where a resistor between VCC and SENSE regulates (VCC - VSENSE) to 47mV when FB is 0.5V or higher, falling to 12mV at FB = 0V.
8 VCC power_in Positive supply input for normal operation from 9V to 80V (ICC typically 2mA), with an internal undervoltage lockout that disables the chip below 8.3V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category TVS/Fuse/Board Level Protection
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Operating Range VCC 9 80 V 2
VCC Supply Current ICC 2 5.5 mA ON = 3V 2
VCC Undervoltage Lockout VLKO 7.5 8.3 8.8 V 2
FB Pin High Voltage Threshold VFBH 1.28 1.313 1.345 V FB Low to High Transition 2
FB Pin Low Voltage Threshold VFBL 1.221 1.233 1.245 V FB High to Low Transition 2
FB Pin Hysteresis Voltage VFBHST 80 mV 2
FB Pin Input Current IINFB -1 µA VFB = GND 2
FB Pin Threshold Line Regulation ∆VFB 0.05 mV/V 9V ≤ VCC ≤ 80V 2
SENSE Pin Trip Voltage (VCC, VSENSE) VSENSETRIP 8 12 17 mV VFB = 0V 2
SENSE Pin Trip Voltage (VCC, VSENSE) VSENSETRIP 39 47 55 mV VFB = 1V 2
GATE Pin Pull-Up Current IGATEUP -5 -10 -20 µA Charge Pump On, VGATE = 7V 2
GATE Pin Pull-Down Current IGATEDN 35 70 100 mA Any Fault Condition, VGATE = 2V 2
External N-Channel Gate Drive ∆VGATE 4.5 18 V VGATE, VCC, VCC = 10.8V to 20V 2
External N-Channel Gate Drive ∆VGATE 10 18 V VGATE, VCC, VCC = 20V to 80V 2
TIMER Pin Pull-Up Current ITIMERUP -24 -80 -132 µA VTIMER = 0V 2
TIMER Pin Pull-Down Current ITIMERON 1.5 3 5 µA VTIMER = 1V 2
ON Pin High Threshold VONH 1.28 1.313 1.345 V ON Low to High Transition 2
ON Pin Low Threshold VONL 1.221 1.233 1.245 V ON High to Low Transition 2
ON Pin Hysteresis VONHYST 80 mV 2
ON Pin Input Current IINON -1 µA VON = GND 2
PWRGD Output Low Voltage VOL 0.4 V IO = 2mA 2
PWRGD Output Low Voltage VOL 2.5 V IO = 4mA 2
PWRGD Pin Leakage Current IOH 10 µA VPWRGD = 80V 2
ON Low to GATE Low Propagation Delay tPHLON 6 µs Figures 1, 2 3
ON High to GATE High Propagation Delay tPLHON 1.7 µs Figures 1, 2 3
FB Low to PWRGD Low Propagation Delay tPHLFB 3.2 µs Figures 1, 3 3
FB High to PWRGD High Propagation Delay tPLHFB 1.5 µs Figures 1, 3 3
(VCC, SENSE) High to GATE Low Propagation Delay tPHLSENSE 0.5 1 2 µs Figures 1, 4 3
Supply Voltage (VCC) VCC -0.3 100 V 2
Input Voltage (SENSE) SENSE -0.3 100 V 2
Input Voltage (TIMER) TIMER -0.3 44 V 2
Input Voltage (FB, ON) FB, ON -0.3 60 V 2
Output Voltage (PWRGD) PWRGD -0.3 100 V 2
Output Voltage (GATE) GATE -0.3 100 V 2
Operating Temperature Range (LT1641-1C) 0 70 °C LT1641-1C 2
Storage Temperature Range -65 150 °C 2
Lead Temperature (Soldering) 300 °C 10 sec 2
Junction-to-Ambient Thermal Resistance θJA 110 °C/W 2
Maximum Junction Temperature TJMAX 125 °C 2

CAD (KiCad official)

  • Symbol: LT1641-1CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 00aa5309da79d653, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF