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LT1464CS8#PBF

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Analog Devices FET Input Amplifiers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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LT1464CS8#PBF

Analog Devices · FET Input Amplifiers · SO-8

LT1464CS8#PBF from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT A output Output of amplifier A, which can swing a 10k load to within 1.5V of either supply according to the datasheet.
2 -IN A input Inverting input of amplifier A, with input bias current of 20pA max (LT1464C) at VS = ±15V.
3 +IN A input Noninverting input of amplifier A; the input common mode range includes the positive rail and the amplifier does not phase-reverse within the supplies.
4 V- power_in Negative supply pin; the datasheet specifies operation on ±5V and ±15V supplies, with a maximum supply of ±20V.
5 +IN B input Noninverting input of amplifier B; the input common mode range includes the positive rail and the amplifier does not phase-reverse within the supplies.
6 -IN B input Inverting input of amplifier B, with input bias current of 20pA max (LT1464C) at VS = ±15V.
7 OUT B output Output of amplifier B, which can swing a 10k load to within 1.5V of either supply according to the datasheet.
8 V+ power_in Positive supply pin; the datasheet specifies operation on ±5V and ±15V supplies, with a maximum supply of ±20V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS 0.4 0.8 mV VS = ±5V 2
Input Offset Voltage VOS 0.6 2 mV VS = ±15V 2
Input Offset Current IOS 0.5 15 pA VS = ±15V 2
Input Bias Current IB -20 0.5 20 pA VS = ±15V 2
Common Mode Rejection Ratio CMRR 74 85 dB VCM = -12.5V to 15V 2
Power Supply Rejection Ratio PSRR 78 90 dB VS = ±2.5V to ±20V 2
Large-Signal Voltage Gain AVOL 300 900 V/mV VO = ±10V, RL = 10k 2
Large-Signal Voltage Gain AVOL 150 450 V/mV VO = ±10V, RL = 2k 2
Large-Signal Voltage Gain AVOL 100 250 V/mV VS = ±5V, VO = ±2V, RL = 10k 2
Large-Signal Voltage Gain AVOL 50 170 V/mV VS = ±5V, VO = ±1V, RL = 2k 2
Output Voltage Swing VOUT 13.5 13.7 V RL = 10k 3
Output Voltage Swing VOUT 13.3 13.5 V RL = 2k 3
Output Voltage Swing VOUT 3.5 3.7 V VS = ±5V, RL = 2k 3
Slew Rate SR 0.5 0.9 V/µs RL = 10k (Note 4) 3
Gain Bandwidth Product GBW 650 1000 kHz f = 10kHz 3
Supply Current per Amplifier IS 145 200 µA VS = ±15V 3
Supply Current per Amplifier IS 135 200 µA VS = ±5V 3
Offset Voltage Match VOS 0.5 1.3 mV VS = ±5V (Note 7) 3
Offset Voltage Match VOS 0.8 3.3 mV VS = ±15V (Note 7) 3
Noninverting Bias Current Match ΔIB+ 0.5 30 pA VS = ±15V (Note 7) 3
Common Mode Rejection Match ΔCMRR 71 85 dB Notes 5, 7 3
Power Supply Rejection Match ΔPSRR 74 88 dB Notes 5, 7 3
Input Offset Voltage VOS 0.5 1.4 mV 0°C ≤ TA ≤ 70°C; VS = ±5V 3
Input Offset Voltage VOS 0.9 2.8 mV 0°C ≤ TA ≤ 70°C; VS = ±15V 3
Average Input Offset Voltage Drift ΔVOS/ΔTemp 7 20 µV/°C 0°C ≤ TA ≤ 70°C (Note 6) 3
Input Offset Current IOS 25 450 pA 0°C ≤ TA ≤ 70°C; VS = ±15V 3
Input Bias Current IB 150 750 pA 0°C ≤ TA ≤ 70°C; VS = ±15V 3
Common Mode Rejection Ratio CMRR 73 85 dB 0°C ≤ TA ≤ 70°C; VCM = -12V to 15V 3
Power Supply Rejection Ratio PSRR 77 89 dB 0°C ≤ TA ≤ 70°C; VS = ±3V to ±20V 3
Large-Signal Voltage Gain AVOL 200 600 V/mV 0°C ≤ TA ≤ 70°C; VO = ±10V, RL = 10k 3
Large-Signal Voltage Gain AVOL 100 350 V/mV 0°C ≤ TA ≤ 70°C; VO = ±10V, RL = 2k 3
Large-Signal Voltage Gain AVOL 80 200 V/mV 0°C ≤ TA ≤ 70°C; VS = ±5V, VO = ±2V, RL = 10k 3
Large-Signal Voltage Gain AVOL 45 150 V/mV 0°C ≤ TA ≤ 70°C; VS = ±5V, VO = ±1V, RL = 2k 3
Output Voltage Swing VOUT 13.4 13.6 V 0°C ≤ TA ≤ 70°C; RL = 10k 3
Output Voltage Swing VOUT 13.2 13.4 V 0°C ≤ TA ≤ 70°C; RL = 2k 3
Output Voltage Swing VOUT 3.4 3.6 V 0°C ≤ TA ≤ 70°C; VS = ±5V, RL = 2k 3
Slew Rate SR 0.4 0.8 V/µs 0°C ≤ TA ≤ 70°C; RL = 10k (Note 4) 3
Gain Bandwidth Product GBW 540 870 kHz 0°C ≤ TA ≤ 70°C; f = 10kHz 3
Supply Current per Amplifier IS 160 220 µA 0°C ≤ TA ≤ 70°C; VS = ±15V 3
Supply Current per Amplifier IS 150 220 µA 0°C ≤ TA ≤ 70°C; VS = ±5V 3
Offset Voltage Match VOS 0.7 2 mV 0°C ≤ TA ≤ 70°C; VS = ±5V (Note 7) 3
Offset Voltage Match VOS 0.9 3.5 mV 0°C ≤ TA ≤ 70°C; VS = ±15V (Note 7) 3
Noninverting Bias Current Match ΔIB+ 35 500 pA 0°C ≤ TA ≤ 70°C (Note 7) 3
Common Mode Rejection Match ΔCMRR 70 84 dB 0°C ≤ TA ≤ 70°C (Notes 5, 7) 4
Power Supply Rejection Match ΔPSRR 73 85 dB 0°C ≤ TA ≤ 70°C (Notes 5, 7) 4
Operating Temperature Range -40 85 °C 2
Specified Temperature Range -40 85 °C 2
Storage Temperature Range -65 150 °C 2
Maximum Junction Temperature TJMAX 150 °C 2
Lead Temperature 300 °C Soldering, 10 sec 2
Supply Voltage -20 20 V 2
Differential Input Voltage -40 40 V 2
Input Current 20 mA 2
Thermal Resistance, Junction-to-Ambient (S8 package) θJA 190 °C/W S8 8-lead plastic SO; TJMAX = 150°C 2

CAD (KiCad official)

  • Symbol: LT1464CS8#PBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: lt1464cs8-pbf-etched.step / lt1464cs8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1464cs8-pbf.step / lt1464cs8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 cfc293376a4accad, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF